HD74LS166AP 查看數據表（PDF） - Renesas Electronics
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HD74LS166AP Datasheet PDF : 8 Pages
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HD74LS166A
Function Table
Clear
Shift
Load
Inputs
Clock
Inhibit
Clock
Serial
Parallel
A…H
Internal outputs
QA
QB
Output
QH
L
X
X
X
X
X
L
L
L
H
X
L
L
X
X
QA0
QB0
QH0
H
L
L
↑
X
a…h
a
b
h
H
H
L
↑
H
X
H
QAn
QGn
H
H
L
↑
L
X
L
QAn
QGn
H
X
H
↑
X
X
QA0
QB0
QH0
Notes: 1. H; high level, L; low level, X; irrelevant
2. ↑; transition from low to high level
3. a to h; the level of steady-state input at inputs A to H respectively
4. QA0 to QH0; the level of QA to QH, respectively, before the indicated steady-state input conditions were
established.
5. QAn to QGn; the level of QA to QG, respectively, before the most recent ↑ transition of the clock.
Rev.4.00, May 10, 2006, page 2 of 7
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