HDD16M64F8-13B 查看數據表（PDF） - Hanbit Electronics Co.,Ltd
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HDD16M64F8-13B
Hanbit Electronics Co.,Ltd
HDD16M64F8-13B Datasheet PDF : 11 Pages
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HANBit
HDD16M64F8
Clock high level width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 tCK
Clock low level width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 tCK
DQS-out access time from CK/CK
tDQSCK
-0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns
Output data access time from CK/CK
tAC
-0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns
Data strobe edge to ouput data edge
tDQSQ
-
+0.6
-
+0.5
-
+0.5 ns
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Data out high impedence time from CK-
tHZQ
-0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns
2
/CK
CK to valid DQS-in
tDQSS
0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQS-in setup time
tWPRES
0
0
0
ns
3
DQS-in hold time
tWPREH
0.25
0.25
0.25
tCK
DQS-in falling edge to CK rising-setup
tDSS
0.2
0.2
0.2
tCK
time
DQS-in falling edge to CK rising hold
tDSH
0.2
0.2
0.2
tCK
time
DQS-in high level width
tDQSH
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
tCK
DQS-in cycle time
tDSC
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Address and Control Input setup time
tIS
1.1
0.9
0.9
ns
Address and Control Input hold time
tIH
1.1
0.9
0.9
ns
Mode register set cycle time
tMRD
16
15
15
ns
DQ & DM setup time to DQS
tDS
0.6
0.5
0.5
ns
DQ & DM hold time to DQS
tDH
0.6
0.5
0.5
ns
DQ & DM input pulse width
tDIPW
2
1.75
1.75
ns
Power down exit time
tPDEX
10
10
10
ns
Exit self refresh to write command
tXSW
116
95
ns
Exit self refresh to bank active
75
75
tXSA
80
ns
command
Exit self refresh to read command
tXSR
200
200
200
Cycle
Refresh interval time
TREF
15.6
15.6
15.6
us
1
Output DQS valid window
TQH
0.35
0.35
0.35
tCK
DQS write postamble time
Notes :
TWPST
0.25
0.25
0.25
tCK
4
1. Maximum burst refresh of 8.
2. tHZQ transitions occurs in the same assess time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving.
3. The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going
from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was
in progress, DQS could be High at this time, depending on tDQSS.
URL : www.hbe.co.kr
REV 1.0(August.2002)
8
HANBit Electronics Co.,Ltd.
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