HDMP-1685A 查看數據表（PDF） - HP => Agilent Technologies

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HDMP-1685A

1.25 Gbps Four Channel SerDes with 5-pin DDR SSTL_2 Parallel Interface

HP => Agilent Technologies 

HDMP-1685A Timing Characteristics – Receiver Sections – Rising and Falling Edge Clocking

TA = 0°C to TC = 85°C, VCC = 3.15 V to 3.45 V

Symbol

Parameter

Units Min. Typ.

f_lock

Frequency Lock at Powerup

µs

B_sync[1,2] Bit Sync Time

bits

tRXS

RX [0:3][0:4] Setup Time (Data Valid Before Clock)

tRXH

RX [0:3][0:4] Hold Time (Data Valid After Clock)

RC [0:3][1] and RC [0:3][0] Duty Cycle

ps

1000

ps

800

%

40

t_rxlat[3]

Receiver Latency

ns

16

bits

20

Max.

500

2500

60

Notes:

1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.

2. Tested using CPLL = 0.1 µF.

3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the

edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC [0:1]).

RC[0:3][0]

or

RC[0:3][1]

RX[0:3][0:4]

RXS

RXH

8 ns

RXS

RXH

Figure 5b. Receiver section parallel output timing using rising and falling edge of either RC[0:3][0] or RC[0:3][1].

SI[0:3]±

RX[0:3][0:4]

10-BIT CHAR B

10-BIT CHAR C

RX[0]

RXLAT

CHAR A[4:0]

CHAR A[9:5]

RX[9]

CHAR B[4:0]

RC[0:3][1]

RC[0:3][0]

Figure 6. Receiver section latency. First bit on serial wire drives RX[0:3][0].

7

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