HDMP-0440 查看數據表（PDF） - HP => Agilent Technologies

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HDMP-0440

Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops

HP => Agilent Technologies 

Pin Definitions

Pin Name

Pin

TO_NODE[0]+ 24

TO_NODE[0]- 25

TO_NODE[1]+ 07

TO_NODE[1]- 06

TO_NODE[2]+ 44

TO_NODE[2]- 43

TO_NODE[3]+ 38

TO_NODE[3]- 37

TO_NODE[4]+ 31

TO_NODE[4]- 30

FM_NODE[0]+ 10

FM_NODE[0]- 09

FM_NODE[1]+ 04

FM_NODE[1]- 03

FM_NODE[2]+ 41

FM_NODE[2]- 40

FM_NODE[3]+ 35

FM_NODE[3]- 34

FM_NODE[4]+ 28

FM_NODE[4]- 27

BYPASS[0]-

14

BYPASS[1]-

15

BYPASS[2]-

16

BYPASS[3]-

17

BYPASS[4]-

18

GND

01

08

11

12

13

19

22

23

33

39

VCCHS[0]

26

VCCHS[1]

05

VCCHS[2]

42

VCCHS[3]

36

VCCHS[4]

29

VCC

02

14

20

21

32

Pin Type Pin Description

HS_OUT Serial Data Outputs: High-speed outputs to a hard disk drive or to a cable.

HS_IN Serial Data Inputs: High-speed inputs from a hard disk drive or from a cable.

I-LVTTL Bypass Inputs: For “disk bypassed” mode, connect BYPASS[n]- to GND

through a 1 kΩ resistor. For “disk in loop” mode, float HIGH.

S

Ground: Normally 0 V. See Figure 9 for Recommended Power Supply Filtering.

S

High Speed Supply: Normally 3.3 V. Used only for high-speed outputs(

S

TO_NODE[n]). See Figure 9 for Recommended Power Supply Filtering.

S

S

S

S

Logic Power Supply: Normally 3.3 V. Used for internal logic. See Figure 9 for

Recommended Power Supply Filtering.

4

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