HDMP-0450 查看數據表（PDF） - HP => Agilent Technologies

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HDMP-0450

Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops

HP => Agilent Technologies 

AC Electrical Specifications

VCC = 3.15 V to 3.45 V

Symbol

Parameter

TLOOP_LAT Total Loop Latency from FM_NODE[0] to TO_NODE[0]

TCELL_LAT Per Cell Latency from FM_NODE[4] to TO_NODE[0]

tr,LVTTLin

Input LVTTL Rise Time Requirement, 0.8 V to 2.0 V

tf,LVTTLin

Input LVTTL Fall Time Requirement, 2.0 V to 0.8 V

tr,LVTTout

Output TTL Rise Time, 0.8 V to 2.0 V, 10 pF Load

tf,LVTTout

Output TTL Fall Time, 2.0 V to 0.8 V, 10 pF Load

trs,HS_OUT HS_OUT Single-Ended Rise Time, 20%-80%

tfs,HS_OUT HS_OUT Single-Ended Fall Time, 20%-80%

trd,HS_OUT HS_OUT Differential Rise Time, 20%-80%

tfd,HS_OUT HS_OUT Differential Fall Time, 20%-80%

VIP,HS_IN

HS_IN Required Peak-to-Peak Differential Input Voltage

VOP,HS_OUT HS_OUT Peak-to-Peak Differential Output Voltage

(Z0 = 75 Ω, Figure 6)

Units Min. Typ. Max.

ns

2.0

ns

0.8

ns

2.0

ns

2.0

ns

1.7 3.3

ns

1.7

2.4

ps

200 300

ps

200 300

ps

200 300

ps

200 300

mV

200 1200 2000

mV

1100 1400 2000

Guaranteed Operating Rates

VCC = 3.15 V to 3.45 V

FC Serial Clock Rate (MBd)

Min.

Max.

1,040

1,080

GE Serial Clock Rate (MBd)

Min.

Max.

1,240

1,260

Figure 4. Eye diagram of TO_NODE[1]± high speed differential output (50 Ω termination).

Note: Measurement taken with a 2^7-1 PRBS input to FM_NODE[1]±.

6

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