HDMP-0482 查看數據表（PDF） - HP => Agilent Technologies

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HDMP-0482

Octal Cell Port Bypass Circuit with CDR and Data Valid Detection

HP => Agilent Technologies 

The HDMP-0482 design allows for

CDR placement at any location

with respect to the hard disk

slots. For example, if the BY-

PASS[0]- pin is floating and hard

disk slots A to G are connected to

PBC cells 1 to 7, respectively, the

CDR function will be performed

before entering the hard disk at

slot A. To obtain a CDR function

after slot G, BYPASS[1]- must be

floating and hard disk slots A to

G must be connected to PBC cells

2,3,4,5,6,7 and 0, respectively.

Table 1 shows all possible

connections.

For configurations where the CDR

is before slot A, a Data Valid

(FM_NODE[0]_DV) pin indicates

whether the incoming data on

FM_NODE[0]± is valid Fibre

Channel data. In addition, an

Amplitude Valid (FM_NODE[7]AV)

pin shows the status of the signal

at FM_NODE[7].

1

2

3

4

5

6

7

0

AV

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

1

CDR

FM_NODE[0]_DV

DV

MODE_VDD

BYPASS0

Figure 1. Block Diagram of HDMP-0482.

FSEL

REFCLK

RFCM

MODE_VDD

BYPASS0

HDMP-0482 Block Diagram

CDR

The Clock and Data Recovery

(CDR) block is responsible for

frequency and phase locking onto

the incoming serial data stream

and resampling the incoming

data based on the recovered

clock. An automatic locking

feature allows the CDR to lock

onto the input data stream

without external training con-

trols. It does this by continually

frequency locking onto the

106.25 MHz reference clock

(REFCLK) and then phase

locking onto the input data

stream. Once bit locked, the CDR

generates a high-speed sampling

clock. This clock is used to

sample or repeat the incoming

data to produce the CDR output.

The CDR jitter specifications

listed in this data sheet assume

an input that has been 8B/10B

encoded.

DV Output

The Data Valid (DV) block detects

if the incoming data on

FM_NODE[0]± is valid Fibre

Channel data. The DV checks for

sufficient K28.5+ characters (per

Fibre Channel framing rules) and

for run length violations (per 8B/

10B encoding) on the data

coming out of the CDR. The

FM_NODE[0]_DV output is

pulled low if a run length viola-

tion (RLV) occurs, or if there are

no commas detected (NCD) in a

sufficient time. It is pulled high if

no errors are found. A RLV error

is defined as any consecutive

sequence of 1s or 0s greater than

five in the serial data bit stream.

A NCD error indicates the

absence of a seven-bit pattern

(0011111) present in the positive

disparity comma (K28.5+)

character. A K28.5+ character

should occur at the beginning of

every Fibre Channel frame of

2148 bytes (or 21480 serial bits),

as well as many times within and

between frames. If this seven-bit

pattern is not found within a 215

bit (~31 µs) interval, an NCD

error is generated.

2

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