HDMP-0482 查看數據表（PDF） - HP => Agilent Technologies
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HDMP-0482 Datasheet PDF : 12 Pages
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Table 3. Pin Definitions for HDMP-0482.
Pin Name Pin Pin Type Pin Description
TO_NODE[0]+ 20
TO_NODE[0]- 19
TO_NODE[1]+ 23
TO_NODE[1]- 22
TO_NODE[2]+ 32
TO_NODE[2]- 31
TO_NODE[3]+ 35
TO_NODE[3]- 34
TO_NODE[4]+ 44
TO_NODE[4]- 43
TO_NODE[5]+ 47
TO_NODE[5]- 46
TO_NODE[6]+ 57
TO_NODE[6]- 56
TO_NODE[7]+ 60
TO_NODE[7]- 59
FM_NODE[0]+ 16
FM_NODE[0]- 15
FM_NODE[1]+ 26
FM_NODE[1]- 25
FM_NODE[2]+ 29
FM_NODE[2]- 28
FM_NODE[3]+ 38
FM_NODE[3]- 37
FM_NODE[4]+ 41
FM_NODE[4]- 40
FM_NODE[5]+ 51
FM_NODE[5]- 50
FM_NODE[6]+ 54
FM_NODE[6]- 53
FM_NODE[7]+ 63
FM_NODE[7]- 62
BYPASS[0]-
13
BYPASS[1]-
24
BYPASS[2]-
30
BYPASS[3]-
36
BYPASS[4]-
42
BYPASS[5]-
49
BYPASS[6]-
55
BYPASS[7]-
1
REFCLK
2
CPLL1
10
CPLL0
11
FM_NODE[7]_AV 14
FM_NODE[0]_DV 4
RFCM
3
MODE_VDD
7
FSEL
12
HS_OUT
Serial Data Outputs: High-speed outputs to a hard disk drive or to a cable input.
HS_IN
Serial Data Inputs: High-speed inputs from a hard disk drive or from a cable output.
I-LVTTL
Bypass Inputs: For “disk bypassed” mode, connect BYPASS[n]- to GND through a1kΩ resistor.
For “disk in loop” mode, float HIGH.
I-LVTTL
C
O-LVTTL
O-LVTTL
I-LVTTL
I_LVTTL
I_LVTTL
Reference Clock: A user-supplied clock reference used for frequency acquisition in
the Clock and Data Recovery (CDR) circuit.
Loop Filter Capacitor: A loop filter capacitor for the internal Clock and Data Recovery (CDR) circuit
must be connected across the CPLL1 and CPLL0 pins. Recommended value is 0.1 µF.
Amplitude Valid: Indicates acceptable signal amplitude on the FM_NODE[7]± inputs.
If (FM_NODE[7]+ - FM_NODE[7]-) >= 400 mV peak-to-peak, FM_NODE[7]_AV = 1
If 400 mV > (FM_NODE[7]+ - FM_NODE[7]-) > 100 mV, FM_NODE[7]_AV = unpredictable
If 100 mV >= (FM_NODE[7]+ - FM_NODE[7]-),
FM_NODE[7]_AV = 0
Data Valid: Indicates valid Fibre Channel Data on the FM_NODE[0]± inputs when HIGH. Indicates
either run length violation error or no comma detected when LOW.
Reference Clock Mode: To configure a one-twentieth-rate reference clock, connect RFCM to
GND through a 1kΩ resistor. To configure a one-tenth-rate reference clock, float RFCM HIGH.
Valid Data Detect Mode: To allow data valid detection, float MODE_VDD HIGH. To configure chip for
“CDR anywhere” capability, connect MODE_VDD to GND through a 1kΩ resistor.
Frame Select: To configure single-frame operation of the data valid and amplitude valid
detection circuits, connect FSEL to GND through a 1k resistor. To configure multi-frame (4-frame)
operation of the data valid and amplitude valid detection circuits, float FSEL HIGH.
Table 3 is continued on next page.
6
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