HEF4006B 查看數據表（PDF） - Philips Electronics
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HEF4006B Datasheet PDF : 5 Pages
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Philips Semiconductors
18-stage static shift register
Product specification
HEF4006B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL MIN TYP MAX
Propagation delays
CP → On
HIGH to LOW
LOW to HIGH
Output transition times
HIGH to LOW
LOW to HIGH
Minimum clock
pulse width; HIGH
Set-up time
Dn → CP
Hold time
Dn → CP
Maximum clock
pulse frequency
5
10
tPHL
15
5
10
tPLH
15
5
10
tTHL
15
5
10
tTLH
15
5
10
tWCPH
15
5
10
tsu
15
5
10
thold
15
5
10
fmax
15
90 180 ns
40
80 ns
30
60 ns
90 180 ns
40
85 ns
35
70 ns
60 120 ns
30
60 ns
20
40 ns
60 120 ns
30
60 ns
20
40 ns
60 30
ns
40 20
ns
30 15
ns
20 10
ns
10
5
ns
5
0
ns
5 −5
ns
5
0
ns
5
0
ns
9 18
MHz
15 30
MHz
18 36
MHz
TYPICAL EXTRAPOLATION
FORMULA
63 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
63 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
see also waveforms Fig.4
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
600 fi + ∑ (foCL) × VDD2
where
10
3200 fi + ∑ (foCL) × VDD2
fi = input freq. (MHz)
15
11 600 fi + ∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
4
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