HEC4031B 查看數據表（PDF） - Philips Electronics

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HEC4031B

64-stage static shift register

Philips Electronics 

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(1) Recirculating input.

(2) Mode control: VDD = recirculation; ground (VSS) = new data.

Fig.5 Cascading using direct clocking for high speed operation (see clock rise and fall time requirements).

(1) Recirculating input.

(2) Mode control: VDD = recirculation; ground (VSS) = new data.

(3) For recirculation mode only, FF to delay data until first register delayed clocking has occurred.

(4) Delayed clock-to-clock; new data into first register.

Fig.6 Cascading using delayed clocking for reduced clock drive requirements.

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