HEF4027B(2008) 查看數據表（PDF） - NXP Semiconductors.
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HEF4027B Datasheet PDF : 13 Pages
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NXP Semiconductors
HEF4027B
Dual JK flip-flop
6. Pinning information
6.1 Pinning
Fig 3. Pin configuration
HEF4027B
2Q 1
2Q 2
2CP 3
2CD 4
2K 5
2J 6
2SD 7
VSS 8
16 VDD
15 1Q
14 1Q
13 1CP
12 1CD
11 1K
10 1J
9 1SD
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6.2 Pin description
Table 2. Pin description
Symbol
Pin
VSS
8
1SD, 2SD
9, 7
1J, 2J
10, 6
1K, 2K
11, 5
1CD, 2CD
12, 4
1CP, 2CP
13, 3
1Q, 2Q
14, 2
1Q, 2Q
15, 1
VDD
16
Description
ground supply voltage
asynchronous set-direct input (active HIGH)
synchronous input
synchronous input
asynchronous clear-direct input (active HIGH)
clock input (LOW-to-HIGH edge-triggered)
complement output
true output
supply voltage
7. Functional description
Table 3. Function table[1]
Inputs
Outputs
nSD
nCD
nCP
nJ
nK
nQ
nQ
H
L
X
X
X
H
L
L
H
X
X
X
L
H
H
H
X
X
X
H
H
HEF4027B_5
Product data sheet
Rev. 05 — 10 November 2008
© NXP B.V. 2008. All rights reserved.
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