HEF4557BP 查看數據表（PDF） - Philips Electronics
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HEF4557BP Datasheet PDF : 7 Pages
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Philips Semiconductors
1-to-64 bit variable length shift register
Product specification
HEF4557B
LSI
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4
VDD
V
SYMBOL MIN. TYP.
Minimum clock
pulse width;
LOW for CP0 or
HIGH for CP1
Minimum reset
pulse width;
HIGH
Set-up times
DA, DB, A/B → CP0,
CP1
L1 to L32 = LOW
L32 = HIGH
Hold times
DA, DB, A/B → CP0,
CP1
L1 to L32 = LOW
L32 = HIGH
Recovery times for MR
L1 to L32 = LOW
L32 = HIGH
Minimum clock
pulse frequency
5
tWCPL
10
or
15
tWCPH
5
10
tWMRH
15
5
10
tsu
15
5
10
tsu
15
5
10
thold
15
5
10
thold
15
5
10
tRMR
15
5
10
tRMR
15
5
10
fmax
15
180
90 ns
60
30 ns
40
20 ns
150
75 ns
70
35 ns
50
25 ns
360 180 ns
140
70 ns
90
45 ns
40 −20 ns
35 −10 ns
30
−5 ns
−40 −110 ns
−10 −45 ns
0 −30 ns
90
30 ns
60
20 ns
50
15 ns
500 250 ns
250 125 ns
150
75 ns
110
50 ns
70
30 ns
60
25 ns
2,5
5 MHz
7
14 MHz
10
20 MHz
see note
Note
1. The set-up, hold and recovery times vary with the minimum number of bits selected. For other values as specified
one may interpolate as shown in the table (see previous page).
January 1995
6
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