HI-8483 查看數據表（PDF） - Holt Integrated Circuits

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HI-8483

ARINC 429 Dual Line Receiver

Holt Integrated Circuits 

HI-8483

PIN DESCRIPTIONS

SIGNAL

CAP1A

CAP1B

CAP2A

CAP2B

GND

IN1A

IN1B

IN2A

IN2B

OUT1A

OUT1B

OUT2A

OUT2B

TESTA

TESTB

+VL

+VS

-VS

FUNCTION

INPUT

INPUT

INPUT

INPUT

POWER

ARINC INPUT

ARINC INPUT

ARINC INPUT

ARINC INPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

INPUT

INPUT

POWER

POWER

POWER

DESCRIPTION

Filter capacitor input for terminal A of channel 1

Filter capacitor input for terminal B of channel 1

Filter capacitor input for terminal A of channel 2

Filter capacitor input for terminal B of channel 2

Chip 0V supply

ARINC 429 input terminal A of channel 1

ARINC 429 input terminal B of channel 1

ARINC 429 input terminal A of channel 2

ARINC 429 input terminal B of channel 2

TTL output terminal A of channel 1

TTL output terminal B of channel 1

TTL output terminal A of channel 2

TTL output terminal B of channel 2

Test input terminal A

Test input terminal B

+5 Volts +/- 10%

+15 Volts +/- 10%

-15 Volts +/- 10%

BLOCK DIAGRAM

+VS

+VL

IN1A

IN1B

CAP1A

CAP1B

TESTA

TESTB

CAP2A

CAP2B

IN2A

IN2B

Bit Detection

and Level

Shifting

Hysteresis

Output

Driver

Channel

Test

Circuitry

Voltage Reference

Threshold

Generator

Bit Detection

and Level

Shifting

Hysteresis

Output

Driver

-VS

GND

FIGURE 1 - HI-8483 BLOCK DIAGRAM

OUT1A

OUT1B

OUT2A

OUT2B

HOLT INTEGRATED CIRCUITS

2

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