HI-8788(2001) 查看數據表（PDF） - Holt Integrated Circuits
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HI-8788
(Rev.:2001)
(Rev.:2001)
Holt Integrated Circuits
HI-8788 Datasheet PDF : 7 Pages
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HI-8787, HI-8788
PIN DESCRIPTIONS
PIN
SYMBOL FUNCTION
28
1, 3-10,13-15, 29-32
11
12
16
17
18
19
20
21
22
23
24
25
26
27
561 SYNC
Dn
GND
A0
SLP1.5
WRITE
RESET
XMIT CLK
XMT RDY
PARITY ENB
V-
TXAOUT
TXBOUT
561 DATA
V+
VCC
digital output
digital inputs
power supply
digital input
digital input
digital input
digital input
digital input
digital output
digital input
power supply
analog output
analog output
digital output
power supply
power supply
DESCRIPTION
ARINC 561 Sync signal
Parallel 16 bit bus input
Ground
Load address, A0=0 for 1st data load, A0=1 for 2nd data load
Selects the slope of the line driver. High=1.5us
Write strobe. Loads data on rising edge.
Registers and sequencing logic initialized when low
Clock input for the transmitter
Goes high if the buffer register is empty
When high the 32nd bit output is odd parity
-10 volt rail
Line driver output - A side
Line driver output - B side
Serial output for ARINC 561 data
+10 volt rail
+5 volt rail, “one” level out of line driver, inverted for “zero”
FUNCTIONAL DESCRIPTION
The HI-8787 is a parallel to serial converter, which when
loaded with two 16 bit parallel words, outputs the data as a
32 bit serial word. Timing circuitry inserts a 4 bit gap at the
end of each 32 bit word. An input buffer register allows load
operations to take place while the previously loaded word
is being transmitted.
If the PARITY ENB pin is high, the 32nd bit will be a parity
bit, inserted so as to make the 32 bit word have odd parity. If
the PARITY ENB pin is low, the 32nd bit will be the D15 bit
of the 2nd word loaded.
Outputs are provided for both ARINC 429 (TXAOUT and
TXBOUT pins), and ARINC 561 (561 DATA and 561 SYNC
pins) type data.
A low signal applied to the RESET pin resets the HI-8787’s
internal logic so that spurious transmission does not take
place during power-up. The registers are cleared so that a
continuous gap will be transmitted until the first word is
loaded into the transmitter.
Input data can be loaded when the XMT RDY signal is
high, which indicates the input buffer register is empty. The
first 16 bit word is loaded with the A0 input high. The sec-
ond word is loaded with A0 in the low state. Each data word
is loaded into the input buffer register by a low pulse on the
WRITE input. (See figure 1). After the second word has
been loaded, the XMT RDY output goes low. The contents
of the input buffer register are transferred to the output reg-
ister during the fourth bit period of the gap. If the fourth gap
bit period of the previous word has already been transmit-
ted, the contents of the input buffer register will be trans-
ferred to the output shift register during the first bit period af-
ter the second data load, and the XMT RDY output goes
high.
After the output shift register is loaded, the data is shifted
out to the output logic in the order shown in figure 2.
The 561 SYNC output pulses low when the XMIT CLK is
low during the 8th bit of the ARINC transmission.
The XMIT CLK frequency is the same as the data rate.
HOLT INTEGRATED CIRCUITS
2
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