HI5860SOICEVAL1 查看數據表（PDF） - Intersil
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HI5860SOICEVAL1 Datasheet PDF : 12 Pages
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HI5860
Absolute Maximum Ratings
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to ACOM. . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D11-D0, CLK, SLEEP) . . . . . . . DVDD + 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA(°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA,
TA = -40°C to +85°C, TA = +25°C for All Typical Values.
TEST CONDITIONS
MIN
MAX
(Note10) TYP (Note 10)
UNITS
SYSTEM PERFORMANCE
Resolution
12
-
-
Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 8)
-2.0
±0.5
+2.0
LSB
Differential Linearity Error, DNL
(Note 8)
-1.0
±0.5
+1.0
LSB
Offset Error, IOS
Offset Drift Coefficient
(Note 8)
(Note 8)
-0.025
-
+0.025 % FSR
-
0.1
-
ppm
FSR/°C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 8)
-10
±2
+10
% FSR
With Internal Reference (Notes 2, 8)
-10
±1
+10
% FSR
Full Scale Gain Drift
With External Reference (Note 8)
-
±50
-
ppm
FSR/°C
With Internal Reference (Note 8)
-
±100
-
ppm
FSR/°C
Full Scale Output Current, IFS
Output Voltage Compliance Range
(Notes 3, 8)
2
-
20
mA
-0.3
-
1.25
V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK
Output Settling Time, (tSETT)
Singlet Glitch Area (Peak Glitch)
Output Rise Time
(Note 3)
±0.05% (±2 LSB) (Note 8)
RL = 25Ω (Note 8)
Full Scale Step
130
-
-
MHz
-
35
-
ns
-
5
-
pV•s
-
2.5
-
ns
Output Fall Time
Full Scale Step
-
2.5
-
ns
Output Capacitance
-
10
-
pF
Output Noise
IOUTFS = 20mA
-
50
-
pA/ √Hz
IOUTFS = 2mA
-
30
-
pA/ √Hz
4
FN4654.7
February 6, 2008
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