HIP4081 查看數據表（PDF） - Intersil

零件编号

产品描述 (功能)

生产厂家

HIP4081

80V/2.5A Peak, High Frequency Full Bridge FET Driver

Intersil 

HIP4081

Pin Descriptions

PIN

NUMBER

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

SYMBOL

BHB

BHI

DIS

VSS

BLI

ALI

AHI

HDEL

LDEL

AHB

AHO

AHS

ALO

ALS

VCC

VDD

BLS

BLO

BHS

BHO

DESCRIPTION

B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-

strap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this

pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI

high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI

high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA

pull-up to VDD will hold BHI high, so no connection is required if high-side and low-side outputs are to be con-

trolled by the low-side input.

Disable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.

When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of

0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold DIS high if this pin is not driven.

Chip negative supply, generally will be ground.

B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected

externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL

(Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels

of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold BLI high if this pin is not driven.

A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected

externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL

(Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels

of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold ALI high if this pin is not driven.

A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI

high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI

high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA

pull-up to VDD will hold AHI high, so no connection is required if high-side and low-side outputs are to be con-

trolled by the low-side input.

High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on de-

lay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guar-

antees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is

approximately 5.1V.

Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay

of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees

no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.

A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-

strap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this

pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

A High-side Output. Connect to gate of A High-side power MOSFET.

A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of

bootstrap capacitor to this pin.

A Low-side Output. Connect to gate of A Low-side power MOSFET.

A Low-side Source connection. Connect to source of A Low-side power MOSFET.

Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap

diodes.

Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).

B Low-side Source connection. Connect to source of B Low-side power MOSFET.

B Low-side Output. Connect to gate of B Low-side power MOSFET.

B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of

bootstrap capacitor to this pin.

B High-side Output. Connect to gate of B High-side power MOSFET.

6

Share Link: