SC1185-1.5ACSW.TR 查看數據表（PDF） - Semtech Corporation

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SC1185-1.5ACSW.TR

PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER

Semtech Corporation 

PROGRAMMABLE SYNCHRONOUS DC/DC

CONVERTER, DUAL LOW DROPOUT

REGULATOR CONTROLLER

SC1185

SC1185A

PRELIMINARY - January 6, 1999

LAYOUT GUIDELINES

Careful attention to layout requirements are necessary

for successful implementation of the SC1185 PWM

controller. High currents switching at 140kHz are pre-

sent in the application and their effect on ground plane

voltage differentials must be understood and mini-

mized.

1). The high power parts of the circuit should be laid out

first. A ground plane should be used, the number and

position of ground plane interruptions should be such

as to not unnecessarily compromise ground plane in-

tegrity. Isolated or semi-isolated areas of the ground

plane may be deliberately introduced to constrain

ground currents to particular areas, for example the in-

put capacitor and bottom FET ground.

2). The loop formed by the Input Capacitor(s) (Cin), the

Top FET (Q1) and the Bottom FET (Q2) must be kept

as small as possible. This loop contains all the high cur-

rent, fast transition switching. Connections should be as

wide and as short as possible to minimize loop induc-

tance. Minimizing this loop area will a) reduce EMI, b)

lower ground injection currents, resulting in electrically

“cleaner” grounds for the rest of the system and c) mini-

mize source ringing, resulting in more reliable gate

switching signals.

3). The connection between the junction of Q1, Q2 and

the output inductor should be a wide trace or copper

region. It should be as short as practical. Since this

connection has fast voltage transitions, keeping this

connection short will minimize EMI. The connection be-

tween the output inductor and the sense resistor should

be a wide trace or copper area, there are no fast volt-

age or current transitions in this connection and length

is not so important, however adding unnecessary

impedance will reduce efficiency.

12V IN

5V

10

1 AGND

GATE2 24

2 GATE1

LDVO 23

3 LDOS1

VID0 22

0.1uF

4 LDOS2

5 VCC

VID1 21

VID2 20

6 REF

VID3 19

0.1uF 7 PWRGOOD

VID4 18

8 CS-

VOSENSE 17

9 CS+

EN 16

10 PGNDH

BSTH 15

11 DH

BSTL 14

12 PGNDL

DL 13

SC1185

Q1

Cin +

1.00k

2.32k

5mOhm

Vout

4uH

Q2

+

Cout

3.3V

+

Cin Lin

Q3

+

Cout Lin1

Heavy lines indicate

Vo Lin1

high current paths.

Q4

+

Cout Lin2

Layout diagram for the SC1185

Vo Lin2

© 1999 SEMTECH CORP.

8

652 MITCHELL ROAD NEWBURY PARK CA 91320

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