5962-88690013A 查看數據表（PDF） - Intersil
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5962-88690013A Datasheet PDF : 8 Pages
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HM-6642
Capacitance TA = +25oC
LIMITS
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
CI
Input Capacitance (Note 2)
-
CO
Output Capacitance (Note 2)
-
10.0
pF
f = 1MHz, All Measurements Reference Device
Ground
12.0
pF
NOTES:
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. Typical derating 5mA/MHz increase in ICCOP.
4. VCC = 4.5V and 5.5V.
Switching Waveform
(9)
TAVEL
(2)
TAVQV
TELAX
(10)
A
ADD VALID
TAVEL (9)
NEXT ADD
(8)
TEHEL
E
TELEL (7)
TELEH
(6)
TEHEL (8)
TELQV
(1)
Q
G
(NOTE)
TGXQZ
(5)
TGVQX
(4)
TGVQV
(3)
DATA VALID
TGXQZ (5)
TIME
REFERENCE
-1 0
1
2
3
NOTE: G has the same timing as G except signal is inverted.
FIGURE 3. READ CYCLE
456
Test Load Circuit
DUT
CL
(NOTE)
NOTE:
TEST HEAD
CAPACITANCE,
INCLUDES STRAY
AND JIG CAPACITANCE
IOH
± 1.5V
IOL
EQUIVALENT CIRCUIT
6-7
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