BR93LC66 查看數據表（PDF） - ROHM Semiconductor

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BR93LC66

4,096-Bit Serial Electrically Erasable PROM

ROHM Semiconductor 

Memory ICs

BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV

(2) Timing in the standby mode

As shown in Figure 8, during standby, if CS rises when

SK is HIGH, the DI state may be read on the rising

edge. If this happens, and DI is HIGH, this is taken to

be the start bit, causing a bit error (see point “a” in

Figure 8).

Make sure all inputs are LOW during standby or when

turning the power supply on or off (see Figure 9).

Point a: Start bit position during erroneous operation

Point b: Actual position of start bit

SK

CS

DI

0

1

a

b

Fig.8 Timing during erroneous operation

SK

CS

DI

0

1

b

Fig.9 Timing during normal operation

(3) Precautions when turning power on and off

When turning the power supply on and off, make sure

CS is set to LOW (see Figure 10).

When CS is HIGH, the EEPROM enters the active

state. To avoid this, make sure CS is set to LOW (dis-

able mode) when turning on the power supply.

(When CS is LOW, all input is cancelled.)

When the power supply is turned off, the low power

state can continue for a long time because of the

capacity of the power supply line. Erroneous opera-

tions and erroneous writing can occur at such times for

the same reasons as described above. To avoid this,

make sure CS is set to LOW before turning off the

power supply.

10

To prevent erroneous writing, these ICs are equipped

with a POR (Power On Reset) circuit, but in order to

achieve operation at a low power supply, VCC is set to

operate at approximately 1.3V. After the POR has been

activated, writing is disabled, but if CS is set to HIGH,

writing may be enabled because of noise or other fac-

tors. However, the POR circuit is effective only when

the power supply is on, and will not operate when the

power is off.

Also, to prevent erroneous writing at low voltages,

these ICs are equipped with a built-in circuit (VCC-lock-

out circuit) which resets the write command if VCC

drops to approximately 2V or lower (typ.).

+ 5V

VCC

GND

+ 5V

CS

GND

Bad example

Good example

(Bad example) Here, the CS pin is pulled up to VCC. In this case, CS is

HIGH (active state). Please be aware that the EEPROM

may perform erroneous operations or write erroneous

data because of noise or other factors. Also, be aware

that this may occur ever if the CS input is at High-2.

(Good example) In this case, CS is LOW when the power supply is turned

on or off.

Fig.10

(4) Clock (SK) rise conditions

If the clock pin (SK) signal of the BR93LC66 / BR93LC-

66A has a long rise time (tr) and if noise on the signal

line exceeds a certain level, erroneous operation can

occur due to erroneous counts in the clock. To prevent

this, a Schmitt trigger is built into the SK input of the

BR93LC66. The hysteresis amplitude of this circuit is

set to approximately 0.2V, so if the noise exceeds the

SK input, the noise amplitude should be set to 0.2VP-P

or lower. Furthermore, rises and falls in the clock input

should be accelerated as much as possible.

(5) Power supply noise

The BR93LC66 discharge high volumes of high voltage

when a write is completed. The power supply may fluc-

tuate at such times. Therefore, make sure a capacitor

of 1000pF or greater is connected between VCC (Pin 8)

and GND (Pin 5).

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