BR93LC66 查看數據表（PDF） - ROHM Semiconductor

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BR93LC66

4,096-Bit Serial Electrically Erasable PROM

ROHM Semiconductor 

Memory ICs

BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV

•Circuit operation

(1) Command mode

With these ICs, commands are not

recognized or acted upon until the

Command

Start Operating

bit code

Address

Data

start bit is received. The start bit is

Read (READ)∗1

1

10

A7 ~ A0

—

taken as the first “1” that is received

after the CS pin rises.

∗1 After setting of the read command

and input of the SK clock, data corre-

sponding to the specified address is

Write Enabled (WEN)

1

Write (WRITE)∗2

1

Write to All Addresses (WRAL)∗2 1

Write Disabled (WDS)

1

00 11XXXXXX —

01

A7 ~ A0 D15 ~ D0

00 01XXXXXX D15 ~ D0

00 00XXXXXX —

output, with data corresponding to up-

Erase (ERASE)∗3

1

11

A7 ~ A0

—

per addresses then output in se-

quence. (Auto increment function)

∗2 When the write or write all address-

Chip Erase (ERAL)∗3

X: Either VIH or VIL

1

00 10XXXXXX —

es command is executed, all data in the selected memory cell is erased automatically, and the input data is written to

the cell.

∗3 These modes are optional modes. Please contact Rohm for information on operation timing.

(2) Operation timing characteristics

(unless otherwise noted, Ta = – 40 to 85°C, VCC = 5V ± 10%)

Parameter

Symbol Min.

SK clock frequency

fSK

—

SK "H" time

tSKH

450

SK "L" time

tSKL

450

CS "L" time

tCS

450

CS setup time

tCSS

50

DI setup time

tDIS

100

CS hold time

tCSH

0

DI hold time

tDIH

100

Data "1" output delay time

tPD1

—

Data "0" output delay time

tPD0

—

Time from CS to output confirmation

tSV

—

Time from CS to output High impedance tDF

—

Write cycle time

tE / W

—

Typ.

—

—

—

—

—

—

—

—

—

—

—

—

—

Max.

1

—

—

—

—

—

—

—

500

500

500

100

10

Unit

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ms

4

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