HM-6504/883 查看數據表（PDF） - Intersil

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HM-6504/883

4096 x 1 CMOS RAM

Intersil 

HM-6504/883

Timing Waveforms

(8)

(7) TELAX

TAVEL

A

ADD VALID

(6)

TEHEL

E

(1) TELQV

(3)

HIGH Z

TELQX

Q

TELEL (18)

TELEH

(5)

(4) TEHQZ

VALID DATA OUTPUT

HIGH

W

TIME

REFERENCE

-1

0

1

2

FIGURE 1. READ CYCLE

(7)

TAVEL

NEXT ADD

TEHEL

(6)

HIGH Z

34

5

TRUTH TABLE

INPUTS

OUTPUT

TIME REFERENCE

E

W

A

Q

FUNCTION

-1

H

X

X

Z

Memory Disabled

0

H

V

Z

Cycle Begins, Addresses are Latched

1

L

H

X

X

Output Enabled

2

L

H

X

V

Output Valid

3

H

X

V

Read Accomplished

4

H

X

X

Z

Prepare for Next Cycle (Same as -1)

5

H

V

Z

Cycle Ends, Next Cycle Begins (Same as 0)

The address information is latched in the on-chip registers

on the falling edge of E (T = 0). Minimum address set up and

hold time requirements must be met. After the required hold

time, the addresses may change state without affecting

device operation. During time (T = 1) the output becomes

enabled but the data is not valid until during time (T = 2). W

must remain high for the read cycle. After the output data

has been read, E may return high (T = 3). This will disable

the output buffer and all input, and ready the RAM for the

next memory cycle (T = 4).

6-139

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