HM-6504/883 查看數據表（PDF） - Intersil
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HM-6504/883 Datasheet PDF : 10 Pages
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HM-6504/883
Timing Waveforms (Continued)
(7)
TAVEL
(8)
TELAX
A
ADD VALID
E
(6)
TEHEL
W
(18) TELEL
(5) TELEH
(10)
(9) TWLEH
TWLWH
(14)
TDVWL
(16)
TWLDX
D
DATA VALID
HIGH Z
Q
(3)
TELQX
(7)
TAVEL
NEXT ADD
(6)
TEHEL
(4)
TEHQZ
HIGH Z
TIME
REFERENCE
TIME
REFERENCE
-1
0
1
2
3
4
5
-1
0
1
2
3
4
5
FIGURE 3. LATE WRITE CYCLE
TRUTH TABLE
INPUTS
OUTPUTS
E
W
A
D
Q
FUNCTION
H
X
X
X
Z
Memory Disabled
H
V
X
Z
Cycle Begins, Addresses are Latched
L
X
V
X
Write Begins, Data is Latched
L
H
X
X
X
Write In Progress Internally
H
X
X
X
Write Completed
H
X
X
X
Z
Prepare for Next Cycle (Same as -1)
H
V
X
Z
Cycle Ends, Next Cycle Begins (Same as 0)
The late write cycle is a cross between the early write cycle
and the read-modify-write cycle.
Recall that in the early write, the output is guaranteed to
remain high impedance, and in the read-modify-write, the
output is guaranteed valid at access time. The late write is
between these two cases. With this cycle the output may
become active, and may become valid data, or may remain
active but undefined. Valid data is written into the RAM if
data setup, data hold, write setup and write pulse widths are
observed.
6-141
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