NVM3060 查看數據表（PDF） - Micronas

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NVM3060

4096-Bit EEPROM

Micronas 

NVM 3060

2. Specifications

2.1. Outline Dimensions

8

5

2.5 . . . 6.4

1

4

max. 9.5

. 0.5 1.1

3 x 2.54

max.

5.08

min. 0.5

min.

2.8

.

15 _

.

. 0.38

.

.

.

. 0_...15 _ .

7.62

Fig. 2–1: NVM 3060 in 8-pin Dil Plastic Package

20 A 8 according to DIN 41870

Weight approx. 0.5 g

Dimensions in mm

2.2. Pin Connections

1 Ground, 0

2 Safe Input S

3 Option Input

4 Reset Input

5 IM Bus Clock Input

6 IM Bus Ident Input

7 IM Bus Data Input/Output

8 Supply Voltage VSUP

2.3. Pin Descriptions

Pin 1 – Ground, 0

This pin must be connected to the negative of the sup-

plies.

Pin 2 – Safe Input S

Fig. 2–2 shows the internal configuration of this input.

Normally, with pin 2 at ground potential (low), one por-

tion of the programming matrix is protected so that this

part of the memory cannot be reprogrammed inadver-

tently. Only when pin 2 receives high potential continu-

ously, the protected portion of the memory matrix can be

programmed. Pin 2 is internally tied to ground via a tran-

sistor equivalent to a 40 kΩ resistor.

Pin 3 – Option Input Fig. 2–2 shows the internal configu-

ration of this input. With pin 3 at ground potential (low)

or floating, the NVM 3060 reacts upon the IM bus ad-

dresses 128,129 and 131. With pin 3 continuously at

VSUP potential (high), the NVM 3060 reacts upon this IM

bus addresses 132,133 and 135 (see Fig.2–6). In this

way, parallel operation of two NVM 3060 is permitted, to

obtain 8192 bits of non-volatile storage directly accessi-

ble via the IM bus. Pin 3 is internally tied to ground via

a transistor equivalent to a 40 kΩ resistor.

Pin 4 – Reset Input

This input has a configuration as shown in Fig. 2–3. Via

this input, the NVM 3060, together with the other circuits

belonging to the system, receives the Reset signal

which is derived from VSUP via an external RC circuit. A

low level is required during power-up and power-down

procedures. Low level at pin 4 (max. 1.3 V) cancels a

programming procedure and an IM bus operation in pro-

gress. The memory address register is not erased. Dur-

ing operation, pin 4 requires high level (min. 2.4 V).

Pins 5 to 7 – IM Bus Connections

These pins serve to connect the NVM 3060 EEPROM

to the IM bus (see section 5.), via which it communicates

with the CCU 2030/2050/2070/3000 Central Control

Units or the SAA 12xx and TVPO 2066 Remote Control

and Tuning ICs. Pins 5 (IM Bus Clock Input) and 6 (IM

Bus Ident Input) are inputs as shown in Fig. 2–3 and pin

7 (IM Bus Data) is an input/output as shown in Fig. 2–4.

The signal diagram for the IM bus is illustrated in Figs.

2–6 and Fig. 5–1. The required addresses which the

NVM 3060 EEPROM receives from the microcomputer,

are also shown in Fig. 2–6.

Pin 8 – Supply Voltage VSUP

The supply voltage required is +5V (±5%), and the cur-

rent consumption in active operation is approx. 30 mA.

Inserting or removing the NVM 3060 from a live socket

may alter programmed data!

4

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