HMP8190 查看數據表（PDF） - Intersil

零件编号

产品描述 (功能)

生产厂家

HMP8190

NTSC/PAL Video Encoder

Intersil 

HMP8190, HMP8191

Controlled Edges

The NTSC and PAL video standards specify edge rates and

rise and fall times for portions of the video waveform. The

HMP8190/HMP8191 automatically implements controlled

edge rates and rise and fall times on these edges:

1. Analog horizontal sync (rising and falling edges)

2. Analog vertical sync interval (rising and falling edges)

3. Color burst envelope

4. Blanking of analog active video

5. Closed captioning information

6. WSS Information

“Sliced” VBI Data

The HMP8190/HMP8191 generates two types of vertical

blanking interval data: closed captioning and widescreen

signalling. The data is generated when enabled in the VBI

data control register. It is placed on the scan lines specified

by the selected output video standard. During scan lines with

VBI data, the pixel inputs are ignored.

Closed Captioning (CC)

The HMP8190/HMP8191 captioning data output includes clock

run-in and start bits followed by the captioning data. During

closed captioning encoding, the pixel inputs are ignored on the

scan lines containing captioning information.

The HMP8190/HMP8191 has two 16-bit registers containing

the captioning information. Each 16-bit register is organized

as two cascaded 8-bit registers. One 16-bit register (caption

21) is read out serially during line 18, 21 or 22; the other

16-bit register (WSS 284) is read out serially during line 281,

284 or 335. The data registers are shifted out LSB first.

The captioning output level is 50 IRE for a logic 1 and 0 IRE

for a logic 0. All transitions between levels are controlled to

have a raised-cosine shape. The rise or fall time of any

transition is 240-288ns.

The caption data registers may be loaded via the I2C interface

or as BT.656 ancillary data. Table 6 illustrates the format of the

caption data as BT.656 ancillary data. The transfer should

occur only once per field before the start of the SAV sequence

of the line containing the captioning output.

When written via the I2C interface, the bytes may be written

in any order but both must be written within one frame time

for proper operation. If the registers are not updated, the

encoder resends the previously loaded values.

The HMP8190/HMP8191 provides a write status bit for each

captioning line. The encoder clears the write status bit to ‘0’

when captioning is enabled and both bytes of the captioning

data register have been written. The encoder sets the write

status bit to ‘1’ after it outputs the data, indicating the

registers are ready to receive new data.

Captioning information may be enabled for either line, both

lines, or no lines. The captioning modes are summarized in

Table 7.

Widescreen Signalling (WSS)

The HMP8190/HMP8191 WSS data output includes clock run-

in and start codes followed by the WSS data. For NTSC

operation, the WSS data is followed by six bits of CRC data.

The HMP8190/HMP8191 has two 14-bit registers containing

the WSS information and two 6-bit registers containing the

WSS CRC data. Each 14-bit register is organized as a 6-bit

register cascaded with an 8-bit one. One 14-bit register (WSS

20) is read out serially during line 17, 20 or 23; the other 14-bit

register (caption 283) is read out serially during line 280, 283

or 336. The data registers are shifted out LSB first.

The WSS output level depends on the video format. For

NTSC operation (EIAJ CPX-1204), the WSS output level is 70

IRE for a logic 1 and 0 IRE for a logic 0. All transitions

between levels are controlled to have a raised-cosine shape

with a rise or fall time of 240ns. For PAL operation (ITU-R

BT.1119), the WSS output level is 71.5 IRE for a logic 1 and 0

IRE for a logic 0. All transitions between levels are controlled

to have a raised-cosine shape with a rise or fall time of 118ns.

The WSS data registers may be loaded via the I2C interface

or as BT.656 ancillary data. Table 8 illustrates the format of

the WSS data as BT.656 ancillary data. The transfer should

occur only once per field before the start of the SAV

sequence of the line containing the WSS output.

When written via the I2C interface, the bytes may be written

in any order but all three bytes of each enabled line must be

written within one frame time for proper operation. If the

registers are not updated, the encoder resends the

previously loaded values.

The HMP8190/HMP8191 provides a write status bit for each

WSS line. The encoder clears the write status bit to ‘0’ when

WSS is enabled and all bytes of the WSS data register have

been written. The encoder sets the write status bit to ‘1’ after

it outputs the data, indicating the registers are ready to

receive new data.

WSS information may be enabled for either line, both lines,

or no lines. The WSS modes are summarized in Table 9.

9

Share Link: