HS7512 查看數據表（PDF） - Signal Processing Technologies

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HS7512

Double–Buffered 12-Bit Multiplying DAC

Signal Processing Technologies 

SPECIFICATIONS

(Typical @ 25°C, nominal power supply, VREF = +10V, unipolar, unless otherwise noted)

PARAMETER

MIN. TYP. MAX.

DIGITAL INPUT

Resolution

2–Quad, Unipolar Coding

12

Binary & Comp. Binary

4–Quad, Bipolar Coding

Logic Compatibility

Offset Binary

CMOS, TTL

UNITS

Bits

Input Current

Data Set-up Time

Strobe Width

Data Hold Time

REFERENCE INPUT

Voltage Range

Input Impedance

ANALOG OUTPUT

Scale Factor

Scale Factor Accuracy

Output Leakage

±1

250

250

0

±25

4

12

62.5

187.5

±0.4

10

µA

ns

ns

ns

V

KOhms

µA/VREF

%

nA

Output Capacitance

COUT 1, all inputs high

COUT 1, all inputs low

COUT 2, all inputs high

COUT 2, all inputs low

STATIC PERFORMANCE

Integral Linearity

SP7512BN/KN, HS3120–2

Differential Linearity

SP7512BN/KN, HS3120–2

Monotonicity

SP7512BN/KN, HS3120–2

STABILITY

Scale Factor

Integral Linearity

Differential Linearity

STABILITY

Monotonicity Temp. Range

SP7512KN, HS3120C–_

SP7512BN

HS3120B–_

80

40

40

80

±0.015

±0.024

Guaranteed to 12 bits

2

0.2

0.2

0

+70

–40

+85

–55

+125

pF

pF

pF

pF

% FSR

%FSR

ppm FSR/°C

ppm FSR/°C

ppm FSR/°C

°C

°C

°C

CONDITIONS

The input coding is comple-

mentary binary if I02 is used.

Digital input voltage must not

exceed supply voltage or go

below –0.5V ; “0” <0.8V;

2.4V < “1” ≤VDD

All strobes are level triggered.

See Timing Diagram; GBD*

All strobes are level triggered.

See Timing Diagram; GBD*

All strobes are level triggered.

See Timing Diagram; GBD*

Using the internal feedback

resistor and an external op

amp.

At 25°C; the output leakage

current will create an offset

voltage at the external op amps

output. It doubles every 10°C

temperature increase.

(T to T )

MIN

MAX

Note 1

(T to T )

MIN

MAX

114

Corporation

SIGNAL PROCESSING EXCELLENCE

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