HS7512 查看數據表（PDF） - Signal Processing Technologies

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HS7512

Double–Buffered 12-Bit Multiplying DAC

Signal Processing Technologies 

PIN ASSIGNMENTS

Pin 1 – FB4 – Feedback Bipolar Operation

Pin 2 – LDTR – Ladder Termination

Pin 3 – FB3 – Feedback Bipolar Operation

Pin 4 – VREF – Reference Voltage Input

Pin 5 – FB1 – Feedback, Unipolar/Bipolar

Pin 6 – IO1 – Current out into virtual ground

Pin 7 – IO2 – Current out-complement of I01

Pin 8 – VSS – Ground, Analog and DAC Register

Pin 9 – DB11 – MSB, Data Bit 1

Pin 10 – DB10 – Data Bit 2

Pin 11 – DB9 – Data Bit 3

Pin 12 – DB8 – Data Bit 4

Pin 13 – DB7 – Data Bit 5

Pin 14 – DB6 – Data Bit 6

Pin 15 – DB5 – Data Bit 7

Pin 16 – DB4 – Data Bit 8

Pin 17 – DB3 – Data Bit 9

Pin 18 – DB2 – Data Bit 10

Pin 19 – DB1 – Data Bit 11

Pin 20 – DB0 – LSB, Data Bit 12

Pin 21 – LDAC – Transfers data from input to

DAC register; a logic “0” latches data into

registers; a logic “1” allows data to change

(transfer to) register.

Pin 22 – CE – Chip Enable, active low

Pin 23 – LBE – Bit 12 to Bit 9 Enable

Pin 24 – MBE – Bit 8 to Bit 5 Enable

Pin 25 – HBE – Bit 4 to Bit 1 Enable

Pin 26 – VDD2 – Supply Analog and DAC

Register

Pin 27 – VSS1 – Ground input latches

Pin 28 – VDD1 – Supply input latches

NOTE: Pins 8 and 27, and pins 26 and 28 must

be connected externally.

116

FEATURES…

The SP7512 and HS3120 are precision 12-bit

multiplying DACs with internal two-stage input

storage registers for easy interfacing with mi-

croprocessor busses. The DACs are implemented

as a one-chip CMOS circuit with a resistor

ladder network designed for 0.01% linearity

without laser trimming.

The input registers are sectioned into 3 seg-

ments of 4 bits each, all individually address-

able. The DAC-register, following the input

registers, is a parallel 12-bit register for holding

the DAC data while the input registers are up-

dated. Only the data held in the DAC register

determines the analog output value of the con-

verter.

The SP7512 and HS3120 have been designed

for great flexibility in connecting to bus-ori-

ented systems. The 12 data inputs are organized

into 3 independent addressable 4-bit input reg-

isters such that the DACs can be connected to

either a 4, 8 or 16-bit data bus. The control logic

of the DACs includes chip enable and latch

enable inputs for flexible memory mapping. All

controls are level-triggered to allow static or

dynamic operation.

A total of 5 output lines are provided on the

DACs to allow unipolar and bipolar output

connection with a minimum of external compo-

nents. The feedback resistor is internal. The

resistor ladder network termination is exter-

nally available, thus eliminating an external

resistor for the 1 LSB offset in bipolar mode.

The SP7512 is available for use in commercial

and industrial temperature ranges, packaged in

V REF

DIGITAL

INPUTS

CE

HBE

MBE

LBE

LDAC

V DD2

400

+15V

V DD1

FB 1

SP7512

I O1

LDTR

FB 4

FB 3

I O2

VSS VSS1

Figure 1. Unipolar Operation

ROS

-

A

+

V OUT

Corporation

SIGNAL PROCESSING EXCELLENCE

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