HT1626 查看數據表（PDF） - Holtek Semiconductor
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HT1626 Datasheet PDF : 21 Pages
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PATENTED
HT1621/HT1621G
Pad Coordinates
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
X
-802.951
-927.055
-927.055
-927.055
-925.358
-925.358
-925.785
-925.785
-925.699
-896.840
-637.515
-452.726
-288.935
-189.915
-84.350
14.669
114.260
213.320
312.380
925.915
925.915
925.915
925.915
925.915
Y
939.295
343.250
244.230
89.374
-52.510
-151.360
-566.516
-675.287
-773.697
-939.537
-935.685
-935.685
-935.685
-935.685
-935.685
-935.685
-940.130
-940.130
-940.130
-867.615
-768.555
-669.495
-570.435
-437.375
Pad No.
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
X
925.915
925.915
925.915
925.915
925.915
925.915
925.915
925.915
849.589
750.530
651.469
552.409
453.349
354.289
255.230
156.169
57.109
-41.951
-141.010
-240.070
-339.130
-438.190
-537.250
-636.310
Unit: mm
Y
-338.315
-239.255
-140.195
-41.134
57.925
156.986
256.046
355.106
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
Pad Description
Pad No.
Pad Name
1
CS
2
RD
3
WR
4
DATA
5
VSS
7
OSCI
6
OSCO
8
9
10
11, 12
13~16
48~17
VLCD
VDD
IRQ
BZ, BZ
COM0~COM3
SEG0~SEG31
I/O
Function
Chip selection input with pull-high resistor
When the CS is logic high, the data and command read from or written to
I the HT1621 are disabled. The serial interface circuit is also reset. But if CS
is at logic low level and is input to the CS pad, the data and command trans-
mission between the host controller and the HT1621 are all enabled.
READ clock input with pull-high resistor
I
Data in the RAM of the HT1621 are clocked out on the falling edge of the RD
signal. The clocked out data will appear on the DATA line. The host control-
ler can use the next rising edge to latch the clocked out data.
WRITE clock input with pull-high resistor
I Data on the DATA line are latched into the HT1621 on the rising edge of the
WR signal.
I/O Serial data input/output with pull-high resistor
¾ Negative power supply, ground
I The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to
generate a system clock. If the system clock comes from an external clock
source, the external clock source should be connected to the OSCI pad. But
O if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads
can be left open.
I LCD power input
¾ Positive power supply
O Time base or WDT overflow flag, NMOS open drain output
O 2kHz or 4kHz tone frequency output pair
O LCD common outputs
O LCD segment outputs
Rev. 2.90
4
November 9, 2010
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