HT16523 查看數據表（PDF） - Holtek Semiconductor

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HT16523

5x7 Dot Character VFD Controller & Driver

Holtek Semiconductor 

HT16523

Command and Data Transfer Methods

Complete access to the VFD driver consists of display

commands and the display data. The number of

transmitted data bytes for a complete access depends

upon the command and memory type as the Command

Table shows. The display control commands and data

are transmitted using a 3-wire serial interface from

the host MCU. The following steps show how the

operation of the serial interface circuitry.

• Setting the CS pin to a “Low” level will enable a

data transfer.

• Data is 8-bits wide and is sequentially shifted-in on

the SI pin from LSB to MSB (LSB first)

• Data shifted into the register is ready at the rising

edge of the serial shift clock, SCK. If the 8-bit

data is to be written in, then internal signals are

automatically generated and the data will be written

into the corresponding register and RAM.

• Setting the CS pin to “High” will disable the

command and data transfer

• When data is written into the RAM area including

DDRAM, ADRAM and CGRAM continuously,

the command used to specify the RAM area is

contained in the first shifted-in command byte

together with the start address. Then the RAM

address will be internally incremented by 1

automatically. Therefore, it is not necessary to

specify the start address of the data to be written

after the command byte.

Reset Function

When the RST pin is set to “Low”, the module is

initialized to the following conditions:

• Address will be reset to 00H for each RAM

including DDRAM, ADRAM and CGRAM

• The contents of the RAM including DDRAM,

ADRAM and CGRAM are undefined.

• All general output ports go “High”.

• Display duty setting will be reset to 8/16 duty

(register value D2, D1, D0=0, 0, 0).

• Number of digits setting will be reset to 16 digits

(register value K2, K1, K0=0, 0, 0).

• All display lights ON/OFF settings will be

switched to the “display off” mode (register value

D,S,H,L=0,0,0,0)

• All segment outputs go “Low”.

• All AD outputs go “Low”.

• All grid outputs go “Low”.

Note: After a power on reset, all the RAM, including

DDRAM, ADRAM and CGRAM, will be

cleared.

Functional Description

Timing Generation Circuit

A timing generation circuit generates timing signals

for the operation of internal circuits such as the

DDRAM, CGRAM, CGROM and ADRAM.

VFD Driver Circuit

The VFD driver circuit consists of 16 grid signal

drivers and 35 segment signal drivers. When the

number of digits are selected by a corresponding

command, the required grid signal drivers

automatically output drive waveforms, while the other

grid signal drivers continue to output non-selection

waveforms. Sending serial data is latched when the

display data character pattern corresponds to the last

address of the display data RAM (DDRAM).

Data Display RAM - DDRAM

The Display Data RAM (DDRAM) stores the display

data in 8-bit character codes. Its extended capacity is

16x8 bits or 16 characters.

DDRAM data write command

Byte R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

1st W 0

0

0

* X3 X2 X1 X0

2nd W C7 C6 C5 C4 C3 C2 C1 C0

3rd W C7 C6 C5 C4 C3 C2 C1 C0

4th W C7 C6 C5 C4 C3 C2 C1 C0

:

:

:

:

:

:

:

:

:

:

*: Don’t care

The DDRAM data write command descriptions are

shown in the following:

• X3~X0: DDRAM address is for 16 digits addressed

from 00H to 0FH

• C7~C0: character code of the CGROM (internal

248 characters) or CGRAM (user-defined 8

characters)

• To specify the character code of the CGROM or

CGRAM continuously, only the character code

needs to be specified

• The addresses of the DDRAM are automatically

incremented by 1.

• The address will be wrapped around to the start

address when the DDRAM data write function is

successively executed and the DDRAM address is

greater than the maximum available address

Rev. 1.00

12

January 18, 2012

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