HT48CA5(2007) 查看數據表（PDF） - Holtek Semiconductor
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HT48CA5 Datasheet PDF : 38 Pages
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HT48RA5/HT48CA5
Functional Description
Execution Flow
The system clock for the MCU is derived from either a
crystal or an RC oscillator. The system clock is internally
divided into four non-overlapping clocks. One instruc-
tion cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of pro-
gram memory.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading register, subroutine call or return from
subroutine, initial reset, internal interrupt, external inter-
rupt or return from interrupts, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed to the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
When a control transfer takes place, an additional
dummy cycle is required.
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m C lo c k
O S C 2 ( R C o n ly )
PC
PC
PC +1
PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*15~*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
00000000 0
0
0
0
0
0
0
0
External Interrupt
00000000 0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow 00000000 0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow 00000000 0
0
0
0
1
1
0
0
Skip
*15~*13 (*12~*0+2)=(within-current bank)
Loading PCL
*15~*8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch
#15~#8
#7
#6
#5
#4
#3
#2
#1
#0
Return (RET, RETI)
S15~S8 S7 S6 S5 S4 S3 S2 S1 S0
Note:
*15~*0: Program counter bits
#15~#0: Instruction code bits
1 bank: 8K words
Program Counter
S15~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.30
6
October 12, 2007
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