HT82V46 查看數據表（PDF） - Holtek Semiconductor
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HT82V46 Datasheet PDF : 27 Pages
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HT82V46
Analog Input Signal Sampling
There are “NM” and “WS” two operating modes of
HT82V46. It can be selected by register bit WS.
“NM” Mode (WS=0; Normal Mode)
The ADCK speed can be specified along with the
ADCK:CDS2 ratio to achieve the desired sample rate
as table 1.
“NM” Mode Timing Diagram
See Figure 2 , Figure 3 and Figure 4.
“WS” Mode (WS=1)
It requires double rate ADCK and pixel rate CDS2
input. CDS1 pin performs same function as RLC/
ACYC pin.
A programmable detect circuit allows the sampling
point derived from CDS2 pin. When set C2DET to
1, the circuit detects either a rising or falling edge
(determined by C2POS control bit) on the CDS2 input
pin and generates an internal INTC2 pulse. When
C2POS=1, a positive edge transition is detected and
when C2POS=0, a falling edge transition is detected.
INTC2 can optionally be delayed by a number of
ADCK periods, specified by the C2DLY[2:0] bits.
Figure 5 shows the sampling point occurs on the first
rising ADCK edge after this internal CDS2 pulse.
“WS” Mode Timing Diagram
See Figure 6 , Figure 7, Figure 8 and Figure 9.
ADCK: 45MHz; CDS: available
ADCK:CDS2
Max. Sample
Rate (MSPS)
3:1
15
2:1
22.5
1:1
45
―
―
―
―
Where X1 : Disable; V1 : Enable
1CH
0
0
1
1
1
Register Bit
2CH CH[1:0]
0
XX
1
XX
00
0
01
10
0
11
1
XX
Red
V1
V1
V1
X1
X1
―
―
R/G/B of PGA
Green
V1
V1
X1
V1
X1
―
―
Blue
V1
X1
X1
X1
V1
―
―
Table 1 “NM” Operating Modes
Mode
3-channel
2-channel
1-channel
Invalid
Invalid
Analog
Input
(R, G, B)
Pixel n
t ADFC1R
Pixel n+1
t C1
Pixel n+2
t PR3
CDS1
t C1FC2R
t C2
CDS2
tADFC2R
t C2FADR
ADCK
OD[7:0]
t ADH
t ADL
t ADC
t OD
t OD
B BR RG GB BR RG GB BR RG GB B R
HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB LB HB
n-4
n-3
n-2
n-1
HB : High Byte; LB : Low Byte
Figure 2 3-channel CDS Analog Input Timing
Rev. 1.10
8
November 24, 2011
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