HV101 查看數據表（PDF） - Supertex Inc

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HV101

3-Pin Hotswap, Inrush Current Limiter Controllers (Negative Supply Rail)

Supertex Inc 

HV100/HV101

Functional Description

Insertion into Hot Backplanes

Telecom, data network and some computer applications

require the ability to insert and remove circuit cards from

systems without powering down the entire system. Since all

circuit cards have some filter capacitance on the power rails,

which is especially true in circuit cards or network terminal

equipment utilizing distributed power systems, the insertion

can result in high inrush currents that can cause damage to

connector and circuit cards and may result in unacceptable

disturbances on the system backplane power rails.

The HV100 and HV101 are designed to facilitate the insertion

and removal of these circuit cards or connection of terminal

equipment by eliminating these inrush currents and powering

up these circuits in a controlled manner after full connector

insertion has been achieved. The HV100 and HV101 are

intended to provide this control function on the negative sup-

ply rail.

Description of Operation

On initial power application the high input voltage internal

regulator seeks to provide a regulated supply for the internal

circuitry. Until the proper internal voltage is achieved all circuits

are held reset by the internal UVLO and the gate to source

voltage of the external N-channel MOSFET is held off. Once

the internal regulator voltage exceeds the UVLO threshold,

the input undervoltage detection circuit (UV) senses the input

voltage to confirm that it is above the internally programmed

threshold. If at any time the input voltage falls below the UV

threshold, all internal circuitry is reset and the GATE output

is pulled down to VNN. UVLO detection works in conjunction

with a power on reset (POR) timer of approximately 3.5ms to

overcome contact bounce. Once the UVLO is satisfied, the

gate is held to VNN until a POR timer expires. Should the UV

monitor toggle before the POR timer expires, the POR timer

will be reset. This process will be repeated each time UVLO

is satisfied until a full POR period has been achieved.

After completion of a full POR period, the MOSFET gate auto-

adapt operation begins. A reference current source is turned

on which begins to charge an internal capacitor generating

a ramp voltage which rises at a slew rate of 2.5 V/ms. This

reference slew rate is used by a closed loop system to gen-

erate a GATE output current to drive the gate of the external

N-channel MOSFET with a slew rate that matches the refer-

ence slew rate. Before the gate crosses a reference voltage,

which is well below the VTH of industry standard MOSFETs,

the pull-up current value is stored and the auto-adapt loop

is opened. This stored pull-up current value is used to drive

the gate during the remainder of the hot swap period. The

result is a normalization with CISS , which for most MOSFETs

scales with CRSS.

The MOSFET gate is charged with a current source until it

reaches its turn on threshold and starts to charge the load

capacitor. At this point the onset of the Miller Effect causes

the effective capacitance looking into the gate to rise, and

the current source charging the gate will have little effect on

the gate voltage. The gate voltage remains essentially con-

stant until the output capacitor is fully charged. At this point

the voltage on the gate of the MOSFET continues to rise to

a voltage level that guarantees full turn on of the MOSFET.

It will remain in the full on state until an input under voltage

condition is detected.

If the circuit attempts turn on into a shorted load, then the

Miller Effect will not occur. The gate voltage will continue to rise

essentially at the same rate as the reference ramp indicating

that a short circuit exists. This is detected by the control circuit

and results in turning off the MOSFET initiating a 2.5 second

delay, after which a normal restart is attempted.

If at any time during the start up cycle or thereafter, the input

voltage falls below the UV threshold the GATE output will

be pulled down to VNN, turning off the N-channel MOSFET

and all internal circuitry is reset. A normal restart sequence

will be initiated once the input voltage rises above the UVLO

threshold plus hysteresis.

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