HV509K6 查看數據表（PDF） - Supertex Inc
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HV509K6 Datasheet PDF : 8 Pages
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Functional Block Diagram
16-bit
Shift
Register
16-bit
Latch
Logic
Level
Translator
Logic
Level
Translator
HV509
Level
Translator
&
Buffer
Function Table
Function
DIN
Inputs
CLK
LE
POL
Outputs
Shift Reg
1 2...16
HV Outputs
1 2...16
BP
DOUT
Load S/R
H OR L
↑
H
X
H or L ●...● ● ●...●
X
●
X
L
L
H
* *..........* * *..........*
L
●
Transfer data in
latch
X
L
L
L
* *..........*
* *..........*
(b)
H
●
X
X
H
H
● ●...●
● ●...●
L
●
Store data in latches
X
X
H
L
● ●...●
● ●...●
(b)
H
●
L
↑
L
H
L ●...●
L ●...●
L
●
Transparent mode
H
↑
L
H
H ●...●
H ●...●
L
●
Invert mode
X
X
H
L
● ●...●
● ●...●
(b)
H
X
X
X
H
H
● ●...●
● ●...●
L
X
Notes:
H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition
● = dependent on previous stage’s state before the last CLK or last LE low
* = data at the last CLK ↑
(b) = bar over all symbols
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