HV6810WG 查看數據表（PDF） - Supertex Inc
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HV6810WG Datasheet PDF : 5 Pages
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Functional Block Diagram
Logic Diagram (positive logic)
Blanking
Latch Enable
Shift Register
Latches
Data Input
Clock
1D
R1
C2 LC1
Q1
C1
2D
HV6810
1D
R2
C2 LC2
Q2
C1
2D
••
••
••
6 Stages
•
• (Q3 thru Q8)
•
•
•
•
not shown
1D
R9
C2 LC9
Q9
C1
2D
1D R10
C2 LC10
Q10
C1
2D
Function Table
Serial
Data
Input
H
L
X
Clock
Input
Shift Register Contents
I1 I2 I3 … IN-1 IN
H R1 R2 … RN-2 RN-1
L R1 R2 … RN-2 RN-1
R1 R2 R3 … RN-1 RN
X X X …X X
Serial
Data
Output
RN-1
RN-1
RN
X
P1 P2 P3 … PN-1 PN
PN
L = Low logic level
H = High logic level
X = Irrelevant
P = Present state
R = Previous state
Strobe
Input
L
H
Latch Contents
I1 I2 I3 … IN-1 IN
R1 R2 R3 … RN-1 RN
P1 P2 P3 … PN-1 PN
X X X …X X
Serial
Out
Blanking
Input
Output Contents
I1 I2 I3 … IN-1 IN
L
P1 P2 P3 … PN-1 PN
H
L L L …L L
Switching Waveforms
t w(CKH)
Clock
50%
50%
Data
t su(D)
Valid
50%
50%
Input Timing
t h(D)
VIH
Clock 50%
Valid
VIL
Input
t CKH–LEH
VIH
VIL
t w(LEH)
Latch
Enable
VIH
50%
VIH
50%
VIL
t pd
Output
VIL
90%
Valid
Output Switching Times
12-145
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