HV9982 查看數據表（PDF） - Supertex Inc

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HV9982

Three-Channel, Closed-Loop, Switch Mode LED Driver IC

Supertex Inc 

HV9982

Functional Description

Power Topology

The HV9982 is a three-channel, switch-mode converter LED

driver designed to control a continuous conduction mode

buck, boost or SEPIC converter in a constant frequency

mode. The IC includes an internal linear regulator, which

operates from input voltages 10V to 40V. The IC can also

be powered directly using the VDD pins and bypassing the

internal linear regulator. The IC includes features typically re-

quired in LED drivers like open LED protection, output short

circuit protection, linear and PWM dimming, programmable

input current limiting and accurate control of the LED cur-

rent. A high current gate drive output enables the controller

to be used in high power converters. The IC is ideally suited

for backlight application using either RGB or multi-channel

white LED configurations.

Power Supply to the IC (VIN, VDD, VDD1-3)

The HV9982 can be powered directly from its VIN pin that

withstands a voltage up to 40V. When a voltage is applied at

the VIN pin, the HV9982 tries to maintain a constant 7.75V

(typ) at the VDD pin. The regulator also has a built in un-

der-voltage lockout which shuts off the IC if the voltage at

the VDD pin falls below the UVLO threshold. By connecting

this VDD pin to the VDD1-3 pins of the three channels, the

internal regulator can be used to power all three channels

in the IC.

The EN pin is a TTL compatible input used to disable the IC.

Pulling the EN pin to GND will shut down the IC and reduce

the quiescent current drawn by the IC to be less than 500μA.

If the enable function is not required, the EN pin can be con-

nected to VDD.

Clock Input (CLK)

The switching frequency of the converters is set by using

a TTL compatible square wave input at the CLK pin. The

switching frequencies of the three converters will be 1/12TH

the frequency of the external clock.

Current Sense (CS1-3)

The current sense input is used to sense the source current

of the switching FET. Each CS input of the HV9982 includes

a built in 100ns (minimum) blanking time to prevent spurious

turn off due to the initial current spike when the FET turns

on.

The IC includes an internal resistor divider network, which

steps down the voltage at the COMP pins by a factor of 15.

This voltage is used as the reference for the current sense

comparators. Since the maximum voltage of the COMP pin

is (VDD - 1.0V), this voltage determines the maximum refer-

ence current for the current sense comparator and thus the

maximum inductor current.

In case the internal regulator is not utilized, an external pow-

er supply (7.0V-9.0V) can be used to power the IC. In this

case, the power supply is directly connected to the VDD1-3

pins and the VIN pin is left unconnected.

All four VDD pins must by bypassed by a low ESR capaci-

tor (≥0.1µF) to provide a low impedance path for the high

frequency current of the output gate driver. These capaci-

tors must be referenced to the individual grounds for proper

noise rejection (see Layout Guidelines section for more in-

formation). Also, in all cases, the four VDD pins must be con-

nected together externally.

The input current drawn from the external power supply (or

VIN pin) is a sum of the 4.5mA (max) current drawn by all the

internal circuitry and the current drawn by the gate drivers

(which in turn depends on the switching frequency and the

gate charge of the external FET).

The current sense resistor RCS should be chosen so that the

input inductor current is limited to below the saturation cur-

rent level of the input inductor. For discontinuous conduction

mode of operation, no slope compensation is necessary. In

this case, the current sense resistor is chosen as:

RCS

=

VDD

13

-

•

1.0V

IIN,pk

where IIN,pk is the maximum desired peak input current.

For continuous conduction mode converters operating in the

constant frequency mode, slope compensation becomes

necessary to ensure stability of the peak current mode con-

troller, if the operating duty cycle is greater than 0.5. This

factor must also be accounted for when determining RCS (see

Slope Compensation section).

Slope Compensation

IIN = 4.5mA + (Qg1 + Qg2 + Qg3) • fS

In the above equation, fS is the switching frequency of the

converters and Qg1-3 are the gate charges of the external

FETs (which can be obtained from the FET datasheets).

Choosing a slope compensation which is one half of the

down slope of the inductor current ensures that the convert-

er will be stable for all duty cycles.

Slope compensation in the HV9982 can be programmed by

two external components (see Fig. 1). A resistor for VDD sets

6

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