M5M54R04AJ-10 查看數據表（PDF） - MITSUBISHI ELECTRIC
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M5M54R04AJ-10 Datasheet PDF : 6 Pages
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MITSUBISHI LSIs
M5M54R04AJ-10,-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
Write cycle (W control mode)
A 0~19
S
OE
VIH
VIL
VIH
VIL
(Note 6)
VIH
VIL
t CW
tsu(S)
tsu(A-WH)
tsu(A)
tw(W)
trec(W)
(Note 6)
W
VIH
VIL
DQ1~4
VIH
(Input Data)
VIL
DQ1~4
VOH
(Output Data)
VOL
tdis(OE)
tsu(D) th(D)
DATA STABLE
tdis(W) (Note 4)
ten(OE) (Note 4)
ten(W)
Hi-Z
Write cycle(S control)
A 0~19
S
W
VIH
VIL
tsu(A)
VIH
VIL
VIH
VIL
(Note 6)
DQ1~4
(Input Data)
DQ1~4
(Output Data)
VIH
VIL
VOH
VOL
ten(S)
(Note 4)
t CW
tsu(S)
trec(W)
tw(W)
tsu(D) th(D)
DATA STABLE
tdis(W)
(Note 4)
Hi-Z
(Note 7)
(Note 6)
Note 6: Hatching indicates the state is don't care.
7: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance.
8: ten,tdis are periodically sampled and are not 100% tested.
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