HX6356PSRC 查看數據表（PDF） - Unspecified
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HX6356PSRC Datasheet PDF : 12 Pages
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HX6356
FUNCTIONAL DIAGRAM
A:0-8,12-13
11
CE
NCS
NWE
NOE
A:9-11, 14
4
Row
•
Decoder
•
•
32,768 x 8
Memory
Array
•••
Column Decoder
Data Input/Output
WE • CS • CE
8
8
DQ:0-7
NWE • CS • CE • OE
(0 = high Z)
1 = enabled
Signal
#
Signal
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
SIGNAL DEFINITIONS
A: 0-14
DQ: 0-7
NCS
NWE
NOE
CE
Address input pins which select a particular eight-bit word within the memory array.
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and
disables all input buffers except CE. If this signal is not used it must be connected to VSS.
Negative write enable, when at a low level activates a write operation and holds the data output drivers in a
high impedance state. When at a high level NWE allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
TRUTH TABLE
NCS
CE
NWE
L
H
H
L
H
L
H
X
XX
X
L
XX
NOE
L
X
XX
XX
MODE
DQ
Read Data Out
Write
Data In
Deselected High Z
Disabled High Z
Notes:
X: VI=VIH or VIL
XX: VSS≤VI≤VDD
NOE=H: High Z output state maintained for
NCS=X, CE=X, NWE=X
2
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