PC133-333-520 查看數據表（PDF） - Infineon Technologies

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PC133-333-520

3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module 3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module 168-Pin Unbuffered DIMM Modules

Infineon Technologies 

HYS 64/72V16300/32220GU

SDRAM-Modules

Operating Currents per SDRAM Component

TA = 0 to 70 oC, VDD = 3.3 V ±0.3 V

Parameter

Operating Current

Test

Condition

–

tRC = tRCMIN., tCK = tCKMIN.

Outputs open, Burst Length = 4, CL = 3

All banks operated in random access,

all banks operated in ping-pong manner

to maximize gapless data access

Precharge Standby Current

in Power Down Mode

tCK = min.

Symbol -7 /7.5 -8

max.

ICC1

160 150

Unit Note

mA 1)

ICC2P

1.5

1.5

mA 1)

CS = VIH (min.), CKE ≤ VIL(MAX)

Precharge Stand-by Current

in Non-Power Down Mode

tCK = min.

ICC2N

40

35

mA 1)

CS = VIH (MIN.), CKE ≥ VIH(MIN)

No Operating Current

tCK = min., CS = VIH(MIN),

active state (max. 4 banks)

CKE ≥ VIH(MIN.) ICC3N

50

45

mA 1)

CKE ≤ VIL(MAX.) ICC3P

10

10

mA 1)

Burst Operating Current

tCK = min.,

Read command cycling

–

ICC4

100 90

mA 1), 2)

Auto-Refresh Current

–

tCK = min.,

Auto-Refresh command cycling

ICC5

230 210 mA 1)

Self-Refresh Current

–

Self-Refresh Mode, CKE = 0.2 V

ICC6

1.5

1.5

mA 1)

1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7 and 7.5 modules

and at 100 Mhz for -8 modules. Input signals are changed once during tCK, except for ICC6 and for standby

currents when tCK = infinity. All values are shown per memory component.

2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3

and BL = 4 assumed and the data-out current is excluded

INFINEON Technologies

8

9.01

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