HYS72T128022GDL-37-C 查看數據表（PDF） - Infineon Technologies
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HYS72T128022GDL-37-C Datasheet PDF : 33 Pages
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HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Preliminary Data Sheet Rev. 0.85 (Apr. 2004)
Low Profile 240-pin Registered DDR2 SDRAM Modules Datasheet
512 MByte, 1 GByte & 2 GByte Modules
PC2-3200R, PC2-4300R
• 240-pin Registered 8-Byte ECC Dual-In-Line
DDR2 SDRAM Module for PC, Workstation
and Server main memory applications
• One rank 64Mb x 72, 128Mb x 72 and
two ranks 128Mb × 72 and 256Mb x 72
organizations
• JEDEC standard Double Data Rate 2
Synchronous DRAMs (DDR2 SDRAMs) with
+ 1.8 V (± 0.1 V) power supply
• Programmable CAS Latencies (3, 4 & 5),
Burst Length (4 & 8) and Burst Type.
• Auto Refresh and Self Refresh
• All inputs and outputs SSTL_1.8 compatible
• Re-drive for all input signals using register
and PLL devices.
• OCD (Off-Chip Driver Impedance
Adjustment) and ODT (On-Die Termination)
• 512MB and 1 GB modulesModules built with • Serial Presence Detect with E2PROM
512Mb DDR2 SDRAMs in 60-ball FBGA
chipsize packages
• Low Profile Modules form factor:
133.35 mm x 30,00 mm (MO-237)
•
Two versions of 2 GB modules
built with 63-ball FBGA dual die chipsize packages
(2 x 512Mb components) or 60-ball FBGA packages
•
Based on JEDEC standard reference card
designs
Performance:
Speed Grade Indicator
Component Speed Grade on Module
Module Speed Grade
Max. Clock Frequency @ CL = 3
Max. Clock Frequency@ CL = 4 & 5
–5
DDR2–400
PC2–3200R
200
200
–3.7
DDR2–533
PC2–4300R
200
266
Unit
MHz
MHz
1.0 Description
The INFINEON HYS72Taaabcd[G/H]R module family are low profile Registered DIMM modules
with 30,00 mm height based on DDR2 technology. DIMMs are available in 64M x 72 (512MByte),
128M x 72 (1GByte) and 256M x 72 (2GByte) organisation and density, intended for mounting into
240 pin connector sockets.
The memory array is designed with 512Mb Double Data Rate (DDR2) Synchronous DRAMs for
ECC applications. All control and address signals are re-driven on the DIMM using register devices
and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one
cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board, which provide
a proper voltage supply impedance over the whole frequency range of operations as number and
values are accordant to the JEDEC specification. The DIMMs feature serial presence detect based
on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to the customer.
2
Rev. 0.85, 2004-04
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