HYS72T256022GDL-5-A 查看數據表（PDF） - Infineon Technologies

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HYS72T256022GDL-5-A

DDR2 Registered Memory Modules

Infineon Technologies 

HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A

Registered DDR2 SDRAM Modules

1.3 Components on Modules and RawCard

DIMM

DRAM components

PLL

Density reference datasheet

Register

Raw Card

512 MB

HYB18T512800AC

1:10, 1.8V, CU877 1:1 25-bit 1.8V SSTU32864

A

HYB18T512800AF

1024 MB HYB18T512800AC

1:10, 1.8V, CU877 1:2 14-bit 1.8V SSTU32864

B

HYB18T512800AF

1024 MB HYB18T512400AC

1:10, 1.8V, CU877 1:2 14-bit 1.8V SSTU32864

C

HYB18T512400AF

2048 MB HYB18T512400AC

tbd.

HYB18T512400AF

tbd.

tbd.

2048 MB HYB18T512400AC

tbd.

HYB18T512400AF

tbd.

tbd.

For a detailed description of all functionalities of the DRAM components on these modules see the referenced component data

sheet

1.4 Pin Definition and Function

Pin Name

Description

Pin Name

Description

A[13:0]

A11, A[9:0]

Row Address Inputs

Column Address Inputs 4)

CB[7:0]

DQS[8:0]

DIMM ECC Check Bits

SDRAM low data strobes

A10/AP

Column Address Input for Auto-

Precharge

DM[8:0] /

DQS[17:9]

SDRAM low data mask/

high data strobes

BA[1:0]

SDRAM Bank Selects

DQS[17:0]

SDRAM differential data strobes

CK0

Clock input

(positive line of differential pair)

SCL

Serial bus clock

CK0

Clock input

(negative line of differential pair)

SDA

Serial bus data line

RAS

Row Address Strobe

SA[2:0]

slave address select

CAS

WE

CS[1:0]

CKE[1:0]

ODT[1:0]

Column Address Strobe

Read/Write Input

Chip Selects 3)

Clock Enable 3)

Active termination control lines 1) 3)

VDD

VREF

VSS

VDDSPD

RESET

Power (+ 1.8 V)

I/O reference supply

Ground

EEPROM power supply

Register and PLL control pin 2)

DQ[63:0]

Data Input/Output

NC

No connection

1) Active termination only applies to DQ, DQS, DQS and DM signals

2) When low, all register outputs will be driven low and the PLL clocks to the DRAM and registers will be set to low levels (the

PLL will remain synchronized with the input clock

3) CS1, ODT1 and CKE1 are used on dual rank modules only

4) Column address A11 is used on modules based on x4 organised 512Mb DDR2 components only.

Data Sheet

Preliminary

4

Rev. 0.85, 2004-04

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