IZ0066-01 查看數據表（PDF） - Integral Corp.
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IZ0066-01 Datasheet PDF : 9 Pages
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DOT MATRIX LCD CONTROLLER & DRIVER
IZ0066
TERMINAL DESCRIPTION
Pin
VDD
VSS
V1 – V5
SEG1– SEG40
COM1– COM16
OSC1
INPUT/OUTPUT
Power
Output
Output
Input
Name
Operating Voltage
Negative Supply Voltage
Segment output
Common output
Oscillator
OSC2
CLK1
CLK2
M
D
Output
Output
Data latch clock
Data shift clock
Alternated signal for LCD
driver output
Display data interface
DESCRIPTION
For logical circuit (+5V ± 10%)
0V(GND)
Bias voltage level for LCD driving
Segment signal output for LCD driving
Common signal output for LCD driving
Both pin connected to Rf resistor or ceramic
resonator for internal oscillator circuit. In case of
external frequency use only, the frequency is input
to OSC1 terminal.
Clock output terminal for the serially transferred
data to be latched to the driver.
Clock output terminal used when D terminal data
output shifts the inside of the driver.
The alternating signal to convert LCD drive
waveform to AC.
Character pattern data, which is corresponding to
each common signal, is supplied to driver serially.
INTERFACE
Power
Supply
LCD
LCD
Resistor or
Ceramic
Resonator
IZ0065
High
Low
Selection
Non selection
E
Input
R/W
Enable
Read/Write
Start anable signal to read or write the data
R/W signal input is used to select the read/write
mode
MPU
High
Low
Read mode
Write mode
RS
Register select
Register selection input
DB0 – DB7
Input/Output
Data interface
High
Low
Data register
and write)
(for read
Instruction register (for
write), Busy flag, address
counter (for read)
Used for data transfer between the MPU and
IZ0066. These terminals are for data bus with
bidirectional three-state.
Initial 4 bit (DB0-DB3) are not used during 4 bit
operation (DB7 can be used as a busy flag)
6
6
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