IC41C16105 查看數據表（PDF） - Unspecified

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IC41C16105

1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

Unspecified 

IC41C16105

IC41LV16105

TRUTH TABLE

.unction

Standby

Read: Word

Read: Lower Byte

RAS

H

L

L

LCAS UCAS WE

H

H

X

L

L

H

L

H

H

OE Address tR/tC

X

X

L ROW/COL

L

ROW/COL

Read: Upper Byte

L

H

L

H

L

ROW/COL

Write: Word (Early Write)

Write: Lower Byte (Early Write)

L

L

L

L

X ROW/COL

L

L

H

L

X ROW/COL

Write: Upper Byte (Early Write)

L

H

L

L

X ROW/COL

Read-Write(1,2)

Hidden Refresh

RAS-Only Refresh

CBR Refresh(4)

L

L

Read(2) L→H→L L

Write(1,3) L→H→L L

L

H

H→L

L

L H→L L→H ROW/COL

L

H

L

ROW/COL

L

L

X ROW/COL

H

X

X

ROW/NA

L

X

X

X

Notes:

1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).

2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).

3. EARLY WRITE only.

4. At least one of the two CAS signals must be active (LCAS or UCAS).

I/O

High-Z

DOUT

Lower Byte, DOUT

Upper Byte, High-Z

Lower Byte, High-Z

Upper Byte, DOUT

DIN

Lower Byte, DIN

Upper Byte, High-Z

Lower Byte, High-Z

Upper Byte, DIN

DOUT, DIN

DOUT

DOUT

High-Z

High-Z

Integrated Circuit Solution Inc.

DR014-0A 06/07/2001

S2-3

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