IC42S32200-7TI 查看數據表（PDF） - Integrated Circuit Systems

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IC42S32200-7TI

512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

Integrated Circuit Systems 

IC42S32200

IC42S32200L

CLK

DQM

T0

T1

T2

T3

T4

T5

T6

T7

T8

COMMAND

NOP

READ A

NOP

NOP

NOP

NOP

WRITE B

NOP

NOP

DQ’s

: "H" or "L"

DOUT A

DINB0

Must be Hi-Z before

the Write Command

DINB1

DINB2

Read to Write Interval (Burst Length = 4,CAS#Latency =3)

CLK

DQM

T0

T1

T2

T3

T4

T5

T6

T7

T8

1 Clk Interval

COMMAND

NOP

NOP

BANKA

ACTIVAT E

NOP

READ A

WRITEA

NOP

NOP

NOP

CAS# latency=2

tCK2, DQs

: "H" or "L"

DIN A0

DIN A1

DIN A2

Read to Write Interval (Burst Length = 4,CAS#Latency =2)

DIN A3

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

DQM

COMMAND

NOP

NOP

READ A

NOP

NOP

WRITEB

NOP

NOP

NOP

CAS# latency=2

tCK2,tCDKQ2’s, DQs

: "H" or "L"

DIN B0

DIN B1

DIN B2

DIN B3

Read to Write Interval (Burst Length = 4,CAS#Latency =2)

A read burst without the auto precharge function may be interrupted by a BankPrecharge/

PrechargeAll command to the same bank.The following figure shows the optimum time that

BankPrecharge/PrechargeAll command is issued in different CAS#latency.

10

Integrated Circuit Solution Inc.

DR036-0D 02/04/2005

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