ICL7116 查看數據表（PDF） - Intersil
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ICL7116 Datasheet PDF : 14 Pages
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ICL7116, ICL7117
a
a
a
a
fb
fbfb
gc
g
g
b
ec
ec ec
d
d
d
7
SEGMENT
DECODE
7
SEGMENT
DECODE
7
SEGMENT
DECODE
TYPICAL SEGMENT OUTPUT
V+
0.5mA
8mA
TO
SEGMENT
DIGITAL GROUND
† THREE INVERTERS
ONE INVERTER SHOWN
FOR CLARITY
LATCH
1000’s
100’s
10’s
1’s
COUNTER COUNTER COUNTER COUNTER
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
V+
CLOCK
†
÷4
LOGIC CONTROL
40
39
38
70kΩ
1
OSC 1
OSC 2
OSC 3
HLDR
35
37
500Ω
21
V+
TEST
DIGITAL
GROUND
FIGURE 8. ICL7117 DIGITAL SECTION
System Timing
Figure 9 shows the clocking arrangement used in the
ICL7116 and ICL7117. Two basic clocking arrangements
can be used:
1. Figure 9A, an external oscillator connected to pin 40.
2. Figure 9B, an R-C oscillator using all three pins.
The oscillator frequency is divided by four before it clocks the
decade counters. It is then further divided to form the three
convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (0 to 2000 counts) and auto-
zero (1000 counts to 3000 counts). For signals less than full
scale, auto-zero gets the unused portion of reference de-
integrate. This makes a complete measure cycle of 4,000
counts (16,000 clock pulses) independent of input voltage.
For three readings/second, an oscillator frequency of 48kHz
would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz, 331/3kHz, etc. should
tion, Oscillator frequencies of
be selected. For 50Hz rejec-
200kHz, 100kHz, 662/3kHz,
50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5
readings/second) will reject both 50Hz and 60Hz (also
400Hz and 440Hz).
INTERNAL TO PART
÷4
CLOCK
40
39
38
GND ICL7117
TEST ICL7116
FIGURE 9A. EXTERNAL OSCILLATOR
INTERNAL TO PART
40
39
R
÷4
38
C
CLOCK
FIGURE 9B. RC OSCILLATOR
FIGURE 9. CLOCK CIRCUITS
9
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