ICM7170MDG 查看數據表（PDF） - Intersil

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ICM7170MDG

Microprocessor-Compatible, Real-Time Clock

Intersil 

Timing Diagrams

ICM7170

A0 - A4, CS

RD

ADDRESS VALID, CS LOW

tAS

tAR

tCYC

tRD

D0 - D7

tACC

OUTPUT DATA VALID

tRX

FIGURE 1. READ CYCLE TIMING FOR NON-MULTIPLEXED BUS (ALE = VIH, WR = VIH)

A0 - A4, CS

WR

D0 - D7

ADDRESS VALID, CS LOW

tAD

tWA

tCYC

tWL

tDW

tWD

INPUT DATA VALID

FIGURE 2. WRITE CYCLE TIMING FOR NON-MULTIPLEXED BUS (ALE = VIH, RD = VIH)

A0 - A4, D0 - D7, CS

ALE

RD

ADDRESS VALID, CS LOW

tLA

tLL

tACC

OUTPUT DATA VALID

tAR

tAL

tCYC

tAS

tRD

FIGURE 3. READ CYCLE TIMING FOR MULTIPLEXED BUS (WR = VIH)

12-9

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