ICS2509C 查看數據表（PDF） - Integrated Circuit Systems

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ICS2509C

3.3V Phase-Lock Loop Clock Driver

Integrated Circuit Systems 

ICS2509C

Electrical Characteristics - Input & Supply

TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-10% (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

Input High Voltage

VIH

Input Low Voltage

VIL

Input High Current

IIH

VIN = VDD

Input Low Current

IIL

VIN = 0 V;

Operating current

IDD1

CL = 0 pF; FIN @ 66M

Input Capacitance

Output Capacitance

CIN1

Logic Inputs

CO1

Logic Outputs

1Guarenteed by design, not 100% tested in production.

MIN

2

VSS-0.3

TYP MAX UNITS

VDD+0.3 V

0.8

V

0.1 100 uA

19

50

uA

140 170 mA

4

pF

8

pF

Timing requirements over recommended ranges of supply

voltage and operating free-air temperature

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Fclk Input clock frequency

25

175

MHz

Input clock frequency

duty cycle

40

60

%

Stabilization time

After power up

1

ms

Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its reference

In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be

Until phase lock is obtained, the specifications for parameters given in the switching characteristics table are not

4

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