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ICS8308AGIT

LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS8308I

LOW SKEW, 1-TO-8

DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER

TABLE 4F. DC CHARACTERISTICS, VDD, VDDO = 2.5V±5%, TA = -40° TO 85°

Symbol Parameter

Test Conditions Minimum Typical

VIH

Input High Voltage

LVCMOS

2

LVCMOS_CLK

-0.3

VIL

Input Low Voltage

CLK_EN, OE

I

Input Current

IN

VIN = VDD or

VIN = GND

VOH

Output High Voltage; NOTE 1

IOH = -15mA

1.8

VOL

Output Low Voltage; NOTE 1

IOL = 15mA

VPP

VCMR

Peak-to-Peak Input Voltage CLK, nCLK

Input Common Mode Voltage;

NOTE 2, 3

CLK, nCLK

0.15

GND + 0.5

NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to VDDO/2.

See Parameter Measurement section, "3.3V Output Load AC Test Circuit".

NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.

NOTE 3: Common mode voltage is defined as V .

IH

Maximum

VDD + 0.3

1.3

0.7

300

0.6

1.3

VDD - 0.85

Units

V

V

V

µA

V

V

V

V

TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40° TO 85°

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

fMAX

Output Frequency

Propagation

tPD

Delay;

CLK, nCLK;

NOTE 1

LVCMOS_CLK;

NOTE 2

IJ 350MHz

IJ 350MHz

2

2

350

MHz

4

ns

4

ns

tsk(o) Output Skew; NOTE 3, 7

Measured on

rising edge @VDDO/2

100

ps

tsk(pp) Part-to-Part Skew; NOTE 4, 7

tR / tF

odc

Output Rise/Fall Time

Output Duty Cycle

Measured on

rising edge @VDDO/2

0.8V to 2V

0.2

IJ 150MHz, Ref = CLK, nCLK

45

1

ns

1

ns

55

%

tPZL, tPZH Output Enable Time; NOTE 5

5

ns

tPLZ, tPHZ

tS

Output Disable Time; NOTE 5

Clock Enable

Setup Time;

NOTE 6

CLK_EN to

CLK, nCLK

CLK_EN to

LVCMOS_CLK

5

ns

1

ns

0

ns

tH

Clock Enable

Hold Time;

NOTE 6

CLK, nCLK to

CLK_EN

LVCMOS_CLK

to CLK_EN

0

ns

1

ns

NOTE 1: Measured from the differential input crossing point to V /2 of the output.

DDO

NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at VDDO/2.

NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with

equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.

NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.

NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.

8308AGI

www.icst.com/products/hiperclocks.html

5

REV. B JULY 25, 2005

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