ICS853014 查看數據表（PDF） - Integrated Circuit Systems

零件编号

产品描述 (功能)

生产厂家

ICS853014

LOW SKEW, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS853014

LOW SKEW, 1-TO-5

2.5V/3.3V DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

TABLE 3A. CONTROL INPUT FUNCTION TABLE

Inputs

Outputs

nEN

CLK_SEL

Selected Source

Q0:Q4

nQ0:nQ4

1

0

PCLK0, nPCLK0

Disabled; LOW

Disabled; HIGH

1

1

PCLK1, nPCLK1

Disabled; LOW

Disabled; HIGH

0

0

PCLK0, nPCLK0

Enabled

Enabled

0

1

PCLK1, nPCLK1

Enabled

Enabled

After nEN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.

In the active mode, the state of the outputs are a function of the PCLK0, nPCLK0 and PCLK1, nPCLK1 inputs as

described in Table 3B.

nPCLK0, nPCLK1

PCLK0, PCLK1

Disabled

Enabled

nEN

nQ0:nQ4

Q0:Q4

FIGURE 1. nEN TIMING DIAGRAM

TABLE 3B. CLOCK INPUT FUNCTION TABLE

Inputs

PCLK0 or PCLK1 nPCLK0 or nPCLK1

Outputs

Q0:Q4

nQ0:nQ4

Input to Output Mode

Polarity

0

1

LOW

HIGH

Differential to Differential

Non Inverting

1

0

HIGH

LOW

Differential to Differential

Non Inverting

0

Biased; NOTE 1

LOW

HIGH

Single Ended to Differential Non Inverting

1

Biased; NOTE 1

HIGH

LOW

Single Ended to Differential Non Inverting

Biased; NOTE 1

0

HIGH

LOW

Single Ended to Differential

Inverting

Biased; NOTE 1

1

LOW

HIGH

Single Ended to Differential

Inverting

NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".

853014BG

www.icst.com/products/hiperclocks.html

3

REV. C MAY 13, 2005

Share Link: