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CS853014BGLFT 查看數據表(PDF) - Integrated Device Technology

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CS853014BGLFT Datasheet PDF : 19 Pages
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ICS853014
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Recommendations for Unused Output Pins
Inputs:
PCLK/PCLK INPUTS
For applications not requiring the use of a differential input, both
the PCLK and PCLK pins can be left floating. Though not required,
but for additional protection, a 1kW resistor can be tied from PCLK
to ground. For applications
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kresistor can be used.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and FOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Zo = 50
FOUT
FIN
Zo = 50
50
RTT =
1
((VOH + VOL) / (VCC – 2)) – 2
Zo
50
VCC - 2V
RTT
Figure 4A. 3.3V LVPECL Output Termination
FOUT
3.3V
125
125
Zo = 50
FIN
Zo = 50
84
84
Figure 4B. 3.3V LVPECL Output Termination
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
11
ICS853014BG REV. DNOVEMBER 12, 2007

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