ICS9169C-40 查看數據表（PDF） - Integrated Circuit Systems
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ICS9169C-40 Datasheet PDF : 6 Pages
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ICS169C-40
Electrical Characteristics at 3.3V
VDD = 3.0 3.7V, TA = 0 70° C unless otherwise stated
PARAMETER
Rise Time1
Fall Time1
Rise Time1
Fall Time1
Duty Cycle1
Duty Cycle1
Jitter, One Sigma1
Jitter, Absolute1
Jitter, One Sigma1
Jitter, Absolute1
Jitter, Cycle to Cycle
(for CPU only)
Input Frequency1
Logic Input Capacitance1
Crystal Oscillator
Capacitance1
Power-on Time1
Frequency Settling Time1
Clock Skew Window1
Clock Skew1
Clock Skew1
AC Characteristics
SYMBOL
Tr1
Tf1
Tr2
Tf2
Dt
Dt
Tj1s1
Tjab1
Tj1s2
TEST CONDITIONS
15pF load, 0.4 to 2.0V; VDD=VDDL
for All Outputs
15pF load, 2.0 to 0.4V; VDD=VDDL
for All Outputs
15pF load, 0.4 to 2.0V; VDDL=2.5V &
VDD = 2.3V; CPU
15pF load, 2.0 to 0.4V; VDDL=2.5V &
VDD = 3.3V; CPU
15pF load CPU, PCI, REF @
VOUT=1.5V
15pF load; VDDL (1:2)=2.5V
VTH=1.25V
CPU & PCI Clocks; Load=15pF,
VDD=VDDL
CPU & PCI Clocks; Load=15pF,
VDD=VDDL
Ref; Load=15pF
Tjab2 Ref Load=15pF
VDD=VDDL; @ 60MHz
VDD=VDDL; @ 66MHz
TCC
VDD=VDDL; @ 75MHz
VDD=3.3V; VDDL=2.5;
for All Frequencies
Fi
CIN Logic input pins
CINX
ton
ts
Tsk1
Tsk2
Tsk3
X1, X2 pins
From VDD=1.6V to 1st crossing of 66.6
MHz VDD supply ramp < 40ms
From 1st crossing of acquisition to <
1% settling
CPU to CPU & PCI to PCI; Load=15pF;
@1.5V
CPU to PCI; Load=15pF; @1.5V;
VDD=VDDL; CPU is early
CPU to PCI; Load=15pF; (CPU is early)
VDDL=2.5V, VTH=1.25V;
VDD=3.3V, VTH=1.5V
MIN
-
-
-
-
45
45
-
-220
-
-500
-400
-350
-250
400
12.0
-
-
-
-
-250
1.0
0.50
TYP
0.9
0.8
1.5
1.4
50
49
50
-
200
-
-
-
-
-
14.318
5
18
2.5
1.8
14.5
2.0
1.5
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
MAX
1.4
1.2
2.0
2.0
55
55
150
220
300
500
+400
350
250
400
16.0
-
-
4.5
2.0
250
4.0
3.0
UNITS
ns
ns
ns
ns
%
%
ps
ps
ps
ps
ps
ps
ps
ps
MHz
pF
pF
ms
ms
ps
ns
ns
4
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