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ICS91718 查看數據表(PDF) - Integrated Circuit Systems

零件编号
产品描述 (功能)
生产厂家
ICS91718
ICST
Integrated Circuit Systems ICST
ICS91718 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
ICS91718
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V
Voltage on any pin with respect to GND . . . . -0.5 to +7.0 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Operating Temperature . . . . . . . . . . . . . . . . . . 0°C to +85°C
Ambient Operating Temperature under Bias . -55 to +125 °C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 0.5 W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Input High Voltage
VIH
2
Input Low Voltage
VIL
VSS - 0.3
Input High Current
IIH VIN = VDD
-5
Input Low Current
IIL1 VIN = 0 V; Inputs with no pull-up resistors
-5
Supply Current
IDD
fIN = 14.318MHz
fIN = 66.66MHz
27
42
Powerdown Current
IDD3.3PD
3
Pin Inductance
Lpin
Pin Capacitance1
CIN Logic Inputs
COUT Output pin capacitance
Transition time1
Ttrans To 1st crossing of target frequency
Settling time1
Ts From 1st crossing to 1% target frequency
Clk Stabilization1
TSTAB From VDD = 3.3 V to 1% target frequency
1
Delay1
tPZH,tPZL Output enable delay (all outputs)
1
1Guaranteed by design, not 100% tested in production.
MAX UNITS
VDD + 0.3 V
0.8
V
5
µA
µA
35
mA
50
mA
5
mA
7
nH
5
pF
6
pF
3
ms
3
ms
3
ms
10
ns
AC Electrical Characteristics
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V ±0.3V
PARAMETER DESCRIPTION
TEST CONDITION
FIN
fOUT
tR
tF
IOD
tID
tJCYC
Input Frequency
Output Frequency
Output Rise Time
Output Fall Time
Output Duty Cycle
Input Duty Cycle
Jitter, Cycle-to-Cycle
Input Clock
Spread Off
15 pF load, 0.8V - 2.4V
15 pF load, 2.4 - 0.8V
15 pf load
0500D—07/15/04
8
MIN TYP
14.318
14.318
0.5
0.5
45
45
MAX
80
80
1
1
55
55
250
UNITS
MHz
MHz
ns
ns
%
%
ps

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