ICS9248YF-50-T(2003) 查看數據表（PDF） - Integrated Circuit Systems

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ICS9248YF-50-T
(Rev.:2003)

Frequency Timing Generator for Pentium II Systems

Integrated Circuit Systems 

ICS9248-50

CPU_STOP# Timing Diagram

ICS9248-50

Notes:

1. All timing is referenced to the internal CPUCLK.

2. CPU_STOP# is an asynchronous input and metastable conditions may

exist. This signal is synchronized to the CPUCLKs inside the ICS9248-50.

3. All other clocks continue to run undisturbed.

4. PD# and PCI_STOP# are shown in a high (true) state.

PCI_STOP# Timing Diagram

ICS9248-50

ICS9248-50

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized

inside the ICS9248.

3. All other clocks continue to run undisturbed.

4. PD# and CPU_STOP# are shown in a high (true) state.

0278I—06/03/03

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